Flash Memory Encoder Architecture for Reduced Circulant Convolution Hardware
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Solution Overview
Problem
Existing encoders in flash memory controllers face increased hardware complexity and cost due to the need for multiple matrix multiplication operations, especially circulant convolution calculations, when the parity-generation matrix is not readily available.
Innovation Solution
The encoder architecture includes a barrel shifter module, calculation circuits, and circulant convolution calculation circuits that process data blocks into partial parity blocks, dividing them into two parts for efficient circulant convolution operations, reducing hardware requirements and allowing for parity generation without the need for an inverse parity-generation matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple matrix multiplication operations and circulant convolution calculations are performed to generate parity, then the encoder can operate without an inverse parity-generation matrix, but the hardware cost and device complexity increase greatly
Solution Approach 1:
The parity blocks are divided into two parts: first parity blocks generated by barrel shifter modules performing matrix multiplication, and second parity blocks generated by circulant convolution calculation circuits. This segmentation allows the system to operate without an inverse parity-generation matrix while reducing the computational burden on any single component, thereby managing hardware complexity.
Solution Approach 2:
The barrel shifter modules perform matrix multiplication operations in advance to generate first parity blocks before the circulant convolution calculation circuits generate second parity blocks. This preliminary action reduces the complexity of subsequent operations and enables the encoder to function without requiring an inverse parity-generation matrix.
2Adaptability or versatility
If multiple matrix multiplication operations are performed to generate parity, then the encoder can function without an inverse parity-generation matrix, but the operation time and productivity decrease
Solution Approach 1:
The encoding process is divided into parallel operations: barrel shifter modules generate first parity blocks through matrix multiplication while circulant convolution calculation circuits simultaneously generate second parity blocks. This segmentation into parallel streams maintains encoding capability without inverse matrix while improving throughput and productivity.
Solution Approach 2:
The encoder merges two different computational approaches (matrix multiplication by barrel shifters and circulant convolution by dedicated circuits) to generate complete parity blocks. This combination maintains operational versatility while the parallel execution of both methods improves encoding speed and productivity.
3Adaptability or versatility
If the parity-generation matrix is not available, then the encoder can still generate parity through multiple operations, but the device complexity and hardware requirements increase
Solution Approach 1:
The encoder architecture is segmented into specialized modules: barrel shifter modules for matrix multiplication operations and circulant convolution calculation circuits for convolution operations. This segmentation enables the system to generate parity without an inverse parity-generation matrix while distributing hardware complexity across dedicated functional units.
Solution Approach 2:
The first parity blocks generated by barrel shifter modules serve as intermediaries that are subsequently processed by circulant convolution calculation circuits to produce final parity blocks. This intermediary structure enables parity generation without direct use of an inverse parity-generation matrix while managing hardware complexity through staged computation.
Data Source
AI summary
For an encoder for use in a flash memory controller, partial parity blocks generated in the encoder are divided into two parts for further operations, wherein a number of partial parity block(s) of the first part generated earlier is less than a number of partial parity block(s) of the second part. The encoder can reduce the hardware required for the circulant convolution calculation in the encoder, and has high efficiency. In addition, by converting a parity-check matrix to generate an isomorphic matrix, some components in the encoder and the decoder can be further omitted, so as to further reduce the manufacturing cost.