Flash Memory Encoder Using Inverse Matrix Parity Generation
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Solution Overview
Problem
Existing encoders for flash memory controllers face high hardware costs due to the complexity of circular convolution calculations required to generate parity, especially when finding a parity generator matrix is challenging, leading to increased complexity and costs.
Innovation Solution
The encoder design includes a barrel shifter module, a first inverse matrix calculating circuit, and a calculating circuit that process data blocks into partial parity blocks, performing inverse matrix calculations to generate parity blocks, reducing the need for circular convolution calculating circuits and thus lowering hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple matrix multiplying operations and compensation/adjustment operations are performed to generate parity, then the parity generation accuracy is improved, but the device complexity and hardware costs greatly increase
Solution Approach 1:
The patent segments the parity generation process into distinct modules: a barrel shifter module for circular convolution operations, an inverse matrix calculating circuit for matrix inversion, and a calculating circuit for final parity computation. This segmentation allows each module to be optimized independently, reducing overall complexity while maintaining accuracy.
Solution Approach 2:
The patent introduces an intermediary inverse matrix calculating circuit that bridges the barrel shifter module and the final calculating circuit. This intermediary component pre-calculates and stores inverse matrix values, eliminating the need for repeated complex matrix multiplying operations during parity generation, thus reducing hardware complexity while preserving accuracy.
2Reliability
If circular convolution calculations are performed to generate parity, then the encoding correctness is ensured, but the hardware costs greatly increase
Solution Approach 1:
The patent performs preliminary action by pre-calculating inverse matrix values using the inverse matrix calculating circuit and storing them for later use. This preliminary computation eliminates the need for repeated circular convolution calculations during actual parity generation, ensuring encoding correctness while significantly reducing hardware requirements and manufacturing costs.
Solution Approach 2:
The patent substitutes the mechanical circular convolution calculation system with an electronic inverse matrix calculation system. Instead of performing repeated circular convolution operations hardware-intensive operations), the system uses pre-computed inverse matrix values in electronic calculations, maintaining encoding correctness while reducing hardware complexity and cost.
Data Source
AI summary
An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.