Encoder, associated encoding method, and flash memory controller utilizing divided partial parity blocks for circulant convolution calculations

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Solution Overview

Problem

The complexity of matrix multiplication operations in encoders for flash memory controllers, particularly circulant convolution calculations, leads to increased hardware costs and complexity, especially when the parity-check generation matrix is not easily found.

Innovation Solution

The encoder design includes a first barrel shifter module, a first computing circuit, an adjusting circuit, a first circulant convolution computing circuit, and a second computing circuit, which process data blocks into partial parity blocks, adjust and perform circulant convolution operations to generate parity blocks, reducing the need for hardware in circulant convolution calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the encoder performs matrix multiplication operations and compensation/adjustment operations to generate parity-check codes when the parity-check generation matrix is not found, then the encoder can still function, but the device complexity and hardware cost increase

Engineering Contradiction:
Improveencoder functionalityVSAvoidhardware cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The encoder divides the parity-check matrix H into two parts: a first part H1 and a second part H2. This segmentation allows the system to pre-store H1 and compute H2 dynamically, reducing the hardware storage requirements while maintaining the ability to generate valid parity-check codes even when a complete pre-computed generation matrix is not available.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-stores the first part H1 of the parity-check matrix in the encoder's memory before actual encoding operations. This preliminary preparation reduces the computational burden during real-time encoding, as H1 is already available and only H2 needs to be computed dynamically based on the received signal.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the encoder performs multiple matrix multiplication operations to generate parity-check codes, then the encoding can be completed, but the calculation complexity and processing time increase

Engineering Contradiction:
Improveencoding completenessVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The parity-check matrix is divided into H1 (pre-stored) and H2 (to be computed). This segmentation reduces the number of matrix multiplication operations needed during real-time encoding, as the system only needs to compute H2 * s2 instead of performing full matrix multiplications with the entire parity-check matrix.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter representation by storing H1 in a fixed format and computing H2 dynamically based on the received signal parameters. This allows the encoder to adapt to different signaling conditions while maintaining efficient computation through parameter-based dynamic generation rather than fixed comprehensive matrix storage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10523243B2Encoder, associated encoding method, and flash memory controller utilizing divided partial parity blocks for circulant convolution calculations
Publication Date: 2019.12.31 SILICON MOTION INC
  • US10523243B2 patent drawing
  • US10523243B2 patent drawing
  • US10523243B2 patent drawing

AI summary

An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.