Flash Storage Erase Scheduling with Buffer-Triggered Early Erase
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Solution Overview
Problem
Flash memory devices in storage devices have slower erase and write speeds compared to read speeds, hindering overall operating efficiency.
Innovation Solution
Implementing a storage device with a memory controller that manages a plurality of nonvolatile memory devices, including a buffer memory, to perform on-time and early erase operations based on specific conditions, such as buffer capacity and time thresholds, to optimize erase operations and reduce performance bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are performed sequentially in all memory blocks before write operations, then data integrity is ensured, but operating speed deteriorates
Solution Approach 1:
The patent performs erase operations in advance during idle periods or when buffer capacity is available, before write operations are requested. The memory controller proactively erases memory blocks and updates the mapping table ahead of time, so that when write operations occur, the destination blocks are already ready to receive data, eliminating the need to wait for erase completion.
Solution Approach 2:
The patent divides memory blocks into different states (available, erasing, erased, unavailable) and manages them independently through a mapping table. This segmentation allows the system to track and manage erased and unerased blocks separately, enabling write operations to proceed to available blocks without waiting for erase operations to complete in other blocks.
2Productivity
If buffer capacity is increased to store more data, then write throughput is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic buffer management where the buffer capacity allocated for erase operations adjusts based on real-time conditions. The memory controller monitors buffer usage and dynamically determines when to perform erase operations - using available buffer space when capacity permits, or delaying erases when buffer is full - thereby optimizing throughput without requiring excessive buffer hardware.
Solution Approach 2:
The memory controller autonomously manages the erase operation scheduling without external intervention. It automatically monitors buffer capacity, selects candidate memory blocks for erasure based on mapping table information, executes erases when conditions are favorable, and updates the mapping table - all without host device involvement, simplifying the overall system architecture.
3Loss of time
If multiple erase operations are performed simultaneously across all memory devices, then total erase time is reduced, but power consumption increases
Solution Approach 1:
The patent performs erase operations partially and selectively rather than simultaneously across all memory blocks. The memory controller identifies specific candidate blocks that are ready for erasure and performs erases on those blocks when conditions permit, rather than initiating erases on all blocks at once. This partial action approach balances speed improvement with power consumption management.
Data Source
AI summary
Disclosed is a storage device which includes nonvolatile memory devices each including a plurality of memory blocks, a memory controller that controls the nonvolatile memory devices, and a buffer memory that buffers data to be written in the nonvolatile memory devices. In an on-time erase operation, the memory controller controls the nonvolatile memory devices such that an erase operation is performed in a memory block for each of the nonvolatile memory devices. When an early erase condition is satisfied, the memory controller selects nonvolatile memory device among the nonvolatile memory devices and controls the selected nonvolatile memory device such that the erase operation is performed in a memory block of the selected nonvolatile memory device. When a free capacity of the buffer memory is smaller than a first threshold value, the memory controller determines that the early erase condition is satisfied.