Flash Storage Erase Scheduling for Buffer-Limited Write Throughput
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Solution Overview
Problem
Flash memory devices exhibit slower erase and write speeds compared to read speeds, hindering the overall operating speed of storage devices due to frequent erase operations.
Innovation Solution
Implement a storage device with a memory controller that manages a plurality of nonvolatile memory devices, performing on-time and early erase operations based on specific conditions, such as buffer memory capacity and time since last erase, to optimize erase operations and reduce performance bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flash memory performs frequent erase operations to write data, then the write capability is improved, but the erase speed becomes a bottleneck that hinders overall operating speed
Solution Approach 1:
The patent performs erase operations in advance before write operations are needed. The memory controller proactively erases memory blocks and updates the mapping table to point to these pre-cleared blocks, so when write operations occur, the destination blocks are already ready to receive data without waiting for erase completion.
Solution Approach 2:
The patent divides the memory system into multiple independent memory blocks that can be erased and managed separately. By segmenting the address space and maintaining separate mapping entries for each block, the system can perform erase operations on individual blocks without affecting others, enabling parallel processing and reducing overall erase impact on write performance.
2Reliability
If the storage device waits for erase operations to complete before writing data, then data integrity is ensured, but the operating speed is reduced due to the slower erase speed
Solution Approach 1:
The system performs erase operations and updates the mapping table in advance, before write operations are initiated. This preliminary preparation ensures that when write operations occur, the mapping information is already valid and the destination blocks are ready, eliminating the need to wait for erase completion while maintaining data integrity through the mapping table validation.
Solution Approach 2:
The patent introduces a mapping table as an intermediary layer between the host and the physical memory blocks. This mapping table abstracts the erase operation status from the write operation, allowing writes to proceed based on logical address mapping without directly depending on the completion status of physical erase operations, thus decoupling the two operations while maintaining integrity.
3Productivity
If the storage device uses a buffer memory to cache write data, then write throughput is improved, but when buffer capacity is limited, erase operations become more frequent and impact performance
Solution Approach 1:
The memory controller proactively manages buffer allocation and triggers erase operations in advance based on predicted write patterns and buffer usage trends. By monitoring buffer consumption and pre-erasing blocks before they are urgently needed, the system reduces the frequency of critical erase operations that would interrupt write throughput, while the mapping table tracks the status of these preliminary erases.
Data Source
AI summary
Disclosed is a storage device which includes nonvolatile memory devices each including a plurality of memory blocks, a memory controller that controls the nonvolatile memory devices, and a buffer memory that buffers data to be written in the nonvolatile memory devices. In an on-time erase operation, the memory controller controls the nonvolatile memory devices such that an erase operation is performed in a memory block for each of the nonvolatile memory devices. When an early erase condition is satisfied, the memory controller selects nonvolatile memory device among the nonvolatile memory devices and controls the selected nonvolatile memory device such that the erase operation is performed in a memory block of the selected nonvolatile memory device. When a free capacity of the buffer memory is smaller than a first threshold value, the memory controller determines that the early erase condition is satisfied.