Flash Memory Erase Coupling Ratio Reduction via Alternating Gate Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory cells, such as NAND and NOR cells, face reduced erase efficiency due to high erase coupling ratios, leading to decreased write-erase endurance as trapped electrons in the inter-poly dielectric layer increase the potential barrier, preventing effective erase operations.
Innovation Solution
The method involves applying alternating voltages to erase gates in flash memory cells, where even or odd erase gates are connected to different voltages, and control gates are grounded or negative, reducing the erase coupling ratio and allowing for continued operation by switching voltage application when initial erase gates fail, thereby improving erase efficiency and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the same erase voltage is applied to all erase gates in an erase block, then the operation is simple and uniform, but the erase efficiency decreases due to high erase coupling ratio
Solution Approach 1:
The erase block is segmented into multiple groups of erase gates (first alternating gates and second alternating gates). Different voltage patterns are applied to different groups sequentially, allowing electrons to be extracted from floating gates through multiple paths. This segmentation reduces the effective erase coupling ratio and improves erase efficiency while maintaining manageable operational complexity through systematic voltage application sequences.
2Reliability
If electrons are trapped in the inter-poly dielectric layer during tunneling, then the potential barrier increases, but this retards electron tunneling and causes erase operation failure
Solution Approach 1:
The method applies preliminary actions by using multiple groups of erase gates with different voltage patterns before the trapped electrons can build up a prohibitive potential barrier. By systematically applying erase voltages to first alternating gates and then second alternating gates, the method extracts electrons through multiple paths, preventing the accumulation of trapped electrons that would otherwise block further erase operations and maintain reliability over multiple write-erase cycles.
Solution Approach 2:
The method changes the voltage parameters applied to different groups of erase gates. By applying different voltage patterns (first voltage pattern to first alternating gates, second voltage pattern to second alternating gates), the method creates multiple electron extraction paths with different potential barriers, allowing electrons to be removed even when some paths become blocked by trapped electrons, thus maintaining erase operation reliability.
3Productivity
If alternating voltages are applied to different erase gates, then the erase coupling ratio is reduced and efficiency improved, but the control complexity increases
Solution Approach 1:
The method employs periodic action by systematically applying voltage patterns to alternating groups of erase gates in a repeating sequence. First alternating gates receive a first voltage pattern, then second alternating gates receive a second voltage pattern, and this sequence repeats. This periodic approach reduces the erase coupling ratio and improves efficiency while maintaining ease of operation through the regular, predictable nature of the voltage application sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances erase efficiency by reducing the erase coupling ratio and extends the write-erase endurance by allowing voltage adjustments and alternating erase paths, ensuring continued functionality of memory cells despite electron trapping.
Implementation Method 1
This type of memory cell is usually erased by tunneling electrons through a layer of inter-poly dielectric from a floating gate to an erase gate
Data Source
AI summary
A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.