Flash Memory Erase Control With Staged Pre-Programming
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Solution Overview
Problem
Erase operations in flash memory devices, particularly those utilizing GIDL erase, face challenges due to non-uniform erasing and reliability issues caused by variations in tunneling rates and physical differences among memory cells, leading to voltage shifts and performance inconsistencies.
Innovation Solution
Implementing a non-uniform pre-programming scheme that separately controls pre-programming operations on word lines and select gate lines during different time periods, using tailored pre-programming techniques to minimize voltage discrepancies and ensure uniform erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional erase operations are applied to memory cell arrays, then erase speed is improved, but non-uniform erasing occurs due to variations in tunneling rates and physical differences among memory cells
Solution Approach 1:
The patent segments the memory cell array into multiple sub-arrays divided by select gate lines, and applies pre-programming operations to different sub-arrays at different times. This segmentation allows tailored control over the erase process for different regions, compensating for variations in tunneling rates and physical characteristics to achieve more uniform erasing across the entire array.
Solution Approach 2:
The patent applies different pre-programming operations to different sub-arrays based on their specific characteristics. By performing pre-programming on first sub-arrays at different times from second sub-arrays, the system adapts the programming parameters to local conditions, ensuring each region receives appropriate treatment for uniform erasure while maintaining overall erase speed.
2Loss of time
If pre-programming operations are performed on all word lines and select gate lines simultaneously, then operation time is reduced, but voltage discrepancies increase leading to non-uniform erasure
Solution Approach 1:
The patent divides the pre-programming operation into sequential phases, where different sub-arrays are programmed at different times. This temporal segmentation allows voltage control to be optimized for each region independently, preventing voltage discrepancies while maintaining reasonable operation time through parallel processing of multiple sub-arrays.
Solution Approach 2:
The patent performs pre-programming operations before the main erase operation on different sub-arrays at different times. This preliminary action prepares each sub-array with appropriate voltage conditions before erasure, ensuring uniform voltage distribution across the array during the subsequent erase process while managing total operation time efficiently.
3Manufacturing precision
If separate pre-programming operations are performed on word lines and select gate lines at different time periods, then erasure uniformity is improved, but operation complexity increases
Solution Approach 1:
The patent segments the memory array by select gate lines into multiple sub-arrays, which simplifies the control complexity by allowing independent management of each sub-array. The peripheral circuit can then systematically apply pre-programming operations to each sub-array in sequence, making the overall process more manageable while achieving uniform erasure across the entire array.
Solution Approach 2:
The patent incorporates verification operations after pre-programming to check the programming status of each sub-array. This feedback mechanism allows the peripheral circuit to adjust subsequent operations based on actual programming results, simplifying control by using measured data to guide the erase process and ensure uniformity without requiring overly complex predictive control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability and performance of memory devices by achieving more consistent erasure and programming characteristics, extending the lifespan and improving data integrity.
Implementation Method 1
performing pre-programming operations on word lines and select gate lines of the memory cell array
Implementation Method 2
variations in tunneling rates and physical differences among memory cells
Implementation Method 3
applying the erase pulse to the source line
Implementation Method 4
particularly those utilizing GIDL erase
Data Source
AI summary
Methods, systems, and apparatus for performing an erase operation in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. Before applying an erase pulse to a source line coupled to the memory cell array, the peripheral circuit separately performs pre-programming operations on word lines and select gate lines of the memory cell array by performing a first pre-programing operation on word lines in a first time period and performing a second pre-programing operation on a first select gate line in a second time period.