NAND Flash Erase Circuit Segmentation for Processing Time Reduction
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Solution Overview
Problem
The increasing complexity and density of NAND-type flash memory devices lead to decreased cell current and increased resistance, resulting in longer processing times during erase sequences, particularly due to the need for intelligent soft program verification operations.
Innovation Solution
The implementation of an erase sequence that alternates between selecting all word lines and only even-numbered or odd-numbered word lines for verification operations, omitting one of the verification steps to reduce ON-resistance and processing time, while ensuring accurate data writing by targeting partial selection memory cell groups based on erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If intelligent soft program verification operation is executed to confirm memory cells are written back, then data writing accuracy is improved, but processing time increases
Solution Approach 1:
The patent divides the memory cell array into two groups based on word line selection: even-numbered word lines and odd-numbered word lines. The verification operation is performed on only one group (e.g., even-numbered) at a time, segmenting the verification process to reduce the number of cells checked in each operation while maintaining overall verification accuracy.
Solution Approach 2:
The patent performs verification on a partial set of memory cells (those connected to even-numbered or odd-numbered word lines) rather than all memory cells. This partial action approach reduces verification time while still providing sufficient confidence in the soft program operation results through subsequent soft program operations that address any remaining over-erased cells.
2Reliability
If all word lines are selected for verification operation, then verification coverage is improved, but ON-resistance increases and processing time increases
Solution Approach 1:
The patent segments the set of word lines into two separate groups: even-numbered word lines and odd-numbered word lines. By selecting only one group at a time for verification operations, the patent reduces the total number of simultaneously active word lines, thereby reducing ON-resistance and processing time while maintaining adequate verification coverage through multiple passes.
Solution Approach 2:
The patent employs periodic verification operations where even-numbered word lines are verified in one cycle and odd-numbered word lines are verified in the next cycle. This periodic action allows the system to maintain lower ON-resistance by limiting the number of simultaneously active word lines while still achieving comprehensive verification coverage over multiple cycles.
Data Source
AI summary
A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.