Flash Memory Erase Verification Using Program Circuitry
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Solution Overview
Problem
Flash memory devices face inefficiencies and inaccuracies in erase verification operations, which are critical for reliability and performance, especially as memory densities increase and more complex erase operations are performed.
Innovation Solution
The implementation of program verification circuitry to perform erase verification operations, utilizing page buffers and combinatorial circuitry to efficiently assess the completion of erase operations and identify any incomplete erasures or damaged cells, thereby reducing the time required for verification and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional verification methods are used for flash memory erase operations, then verification accuracy can be maintained, but verification time increases and system performance deteriorates
Solution Approach 1:
The patent applies preliminary action by performing verification-related preparations during the erase operation itself. The verification circuitry is activated and configured before the actual verification read operation, and page buffer status is tracked throughout the erase process. This allows the verification to be completed much faster since the circuitry and data are already in position, eliminating the need for slow post-erase scanning of all memory cells.
Solution Approach 2:
The patent uses page buffers as intermediaries between the memory array and the verification circuitry. Instead of directly reading and verifying every memory cell, the system uses page buffers to hold and pre-process verification data. The combinatorial circuitry then evaluates the buffered data to determine erase completion, significantly reducing the time required compared to direct cell-by-cell verification.
2Reliability
If comprehensive erase verification is performed to ensure reliability, then accuracy improves, but device complexity and processing overhead increase
Solution Approach 1:
The patent applies partial action by verifying only the necessary portions of erased memory rather than performing exhaustive verification of all cells. The combinatorial circuitry evaluates page buffer status and verifies only those pages that were actually erased or modified, skipping already-verified or unaffected pages. This maintains reliability while reducing the complexity and overhead of the verification process.
Solution Approach 2:
The verification circuitry is integrated within the flash memory device itself, allowing the device to perform self-verification without requiring external controller intervention for the actual verification operations. The device uses its own page buffers and combinatorial logic to autonomously determine erase completion, reducing the burden on external systems and simplifying the overall verification architecture.
3Quantity of substance
If memory density is increased to improve storage capacity, then storage efficiency improves, but erase verification accuracy and reliability deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the large-capacity memory into manageable page buffer units for verification purposes. Each page buffer handles a specific segment of memory, and the combinatorial circuitry evaluates each segment independently. This segmentation approach maintains verification accuracy even in high-density memory by breaking down the complex verification task into smaller, more reliable unit operations that can be processed independently.
Solution Approach 2:
The patent introduces a new dimension of verification by adding combinatorial circuitry that evaluates page buffer status in parallel with the erase operation. Instead of sequential verification in the traditional time dimension, the system uses spatial parallelism through multiple page buffers and combinatorial logic units that can simultaneously evaluate different memory segments, maintaining accuracy across increased storage capacity.
Data Source
AI summary
Example embodiments for verifying an erase operation for a flash memory device may comprise, for one or more embodiments, utilizing program operation verification circuitry to verify, at least in part, the erase operation.