NAND Flash Memory Erase Verify Level Control Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND flash memory devices, repeated write/erase operations lead to variations in memory cell characteristics, resulting in decreased erase operation speed and increased occurrence of erase defects, which can render memory cells defective.
Innovation Solution
A semiconductor memory device with a control method that includes a memory cell array, a voltage generating circuit, and a control circuit. The control circuit checks if the pulse number of the erase voltage exceeds a reference pulse number, and if so, adjusts the erase verify level by changing a parameter to ensure effective erase operations, thereby detecting and mitigating cell deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write/erase operations are repeated to increase memory capacity utilization, then memory usage efficiency is improved, but memory cell characteristics vary and erase operation speed decreases
Solution Approach 1:
The patent applies dynamics by making the erase verify level adjustable rather than fixed. The control circuit dynamically changes the erase verify level based on the number of erase pulses applied, allowing the system to adapt to varying memory cell characteristics after repeated write/erase operations, thereby maintaining effective erase operations despite speed degradation
Solution Approach 2:
The patent changes the parameter of erase verify level to resolve the contradiction. By increasing the erase verify level when the number of erase pulses exceeds a reference value, the system compensates for the decreased erase operation speed and ensures complete erase operations even after repeated rewrite cycles
2Speed
If erase voltage is stepped up to maintain erase speed, then erase operation speed is improved, but the number of pulses is limited and erase defects occur
Solution Approach 1:
The patent implements feedback by monitoring the number of erase pulses applied and using this information to adjust the erase verify level. The control circuit counts the number of erase pulses and compares it with a reference pulse number, then adjusts the erase verify level accordingly to ensure complete erase operations without exceeding voltage limits
Solution Approach 2:
The patent changes the erase verify level parameter in response to the number of pulses applied. When the pulse count exceeds the reference value, the erase verify level is increased to ensure that erase operations are completed effectively, preventing erase defects while operating within voltage constraints
3Productivity
If the number of rewrite operations increases to utilize more memory capacity, then memory utilization is improved, but the number of defective elements increases
Solution Approach 1:
The patent applies preliminary action by adjusting the erase verify level before potential erase defects occur. The control circuit monitors the number of erase pulses and proactively increases the erase verify level when the pulse count approaches or exceeds the reference value, preventing erase defects before they happen and reducing defective elements
Solution Approach 2:
The patent uses feedback from the pulse count monitoring to adjust the erase verify level, ensuring that erase operations remain effective even after numerous rewrite cycles. This feedback mechanism allows the system to maintain reliability and reduce defective elements while maximizing memory utilization
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.