Adaptive Flash Memory Erase Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory integrated circuits face inefficiencies in erase operations, leading to prolonged erase times and increased endurance testing due to variability in erase times across memory blocks, resulting in some blocks taking excessively long to erase, which can lead to chip scrapping and reduced lifespan.
Innovation Solution
The implementation of adaptive erase voltage methods, where a table of adaptive erase voltages is constructed based on erase times to select the optimal voltage for each flash block, and the adaptive erase voltage is written into the memory block for future use, allowing for consistent and rapid erasure across all blocks, even as the number of write and read cycles increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed erase voltage is used for all flash memory blocks, then the erase operation is simple to implement, but erase times vary significantly across blocks causing some blocks to take excessively long and leading to chip scrapping
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the erase voltage based on the measured erase time of each flash memory block. A table of adaptive erase voltages is constructed where different voltage levels correspond to different erase time ranges. After an initial erase operation, the actual erase time is measured and used to select an optimized voltage from the table for subsequent operations, thereby resolving the contradiction between simple implementation and consistent erase performance.
Solution Approach 2:
The patent implements feedback by measuring the actual erase time of each flash block and using this information to select an appropriate erase voltage from a preconstructed adaptive voltage table. The measured erase time serves as feedback that guides the selection of the next erase voltage, creating a closed-loop system that continuously optimizes erase performance while ensuring all blocks meet timing specifications.
2Speed
If higher erase voltage is applied to reduce erase time, then erase speed improves, but the variability in erase times across blocks increases leading to more blocks exceeding maximum time limits
Solution Approach 1:
The patent resolves this contradiction by changing the voltage parameter dynamically rather than using a fixed high voltage. The adaptive voltage table provides multiple voltage levels that can be selected based on the specific erase time characteristics of each block, allowing optimization of erase speed while maintaining consistent timing across all blocks.
Solution Approach 2:
The patent applies local quality by tailoring the erase voltage to the specific characteristics of each flash memory block. Instead of applying a uniform high voltage to all blocks, the system measures each block's erase time and selects a voltage level from the adaptive table that is appropriate for that specific block's performance characteristics, thereby achieving both speed and precision.
3Reliability
If adaptive erase voltage tables are constructed and stored in each memory block, then erase time consistency improves, but device complexity increases due to additional memory structures and calibration procedures
Solution Approach 1:
The patent applies preliminary action by preconstructing the adaptive erase voltage tables during the manufacturing calibration process. The tables are stored in dedicated memory structures within each flash block before the product reaches the customer. This preliminary preparation eliminates the need for complex real-time calculations during operation, achieving reliable erase time compliance while keeping the operational device relatively simple.
Solution Approach 2:
The patent uses copying by storing precomputed voltage lookup tables in each flash memory block. Rather than implementing complex real-time optimization algorithms, the system copies the measured performance characteristics into a simple voltage table that can be quickly referenced during erase operations, thereby achieving reliability without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces erase times for all blocks to under one second, prevents chip scrapping by ensuring all blocks meet erase time specifications, and prolongs the lifespan of flash memory by maintaining performance throughout the targeted lifetime.
Implementation Method 1
During an erase operation, a high voltage is applied between the control gate and the isolated pwell, causing electrons to be removed from the floating gate through Fowler-Nordheim tunneling
Data Source
AI summary
A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.