NAND Flash Memory Erase Voltage Distribution
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Solution Overview
Problem
The high magnitude of erase voltages applied in NAND flash memory devices is stressful and poses reliability concerns for the periphery circuitry, requiring complex high-voltage isolation techniques and larger circuitry designs.
Innovation Solution
The solution involves reducing the magnitude of erase voltages applied to the data lines and source by increasing the voltage levels on access lines during the erase operation, allowing for a more efficient and less stressful erase process without altering the design rules for access lines, thereby reducing the size of the periphery circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high magnitude erase voltages are applied to data lines and source, then erase operation is effective, but reliability of periphery circuitry deteriorates and device complexity increases
Solution Approach 1:
The patent changes the voltage distribution parameters during erase operation: instead of applying high voltage to data lines and source, it applies high voltage to access lines (word lines) while reducing voltage on data lines and source. This parameter redistribution maintains erase effectiveness while reducing stress on periphery circuitry, eliminating the need for complex high-voltage isolation techniques.
2Productivity
If high magnitude erase voltages are applied to data lines and source, then erase operation is effective, but the size of periphery circuitry increases
Solution Approach 1:
The patent redistributes voltage parameters during erase operation to apply high voltage to access lines rather than data lines and source. This maintains erase effectiveness (productivity) while reducing the voltage stress on periphery circuitry, thereby reducing the required size of isolation structures and overall periphery circuitry area.
3Reliability
If high magnitude erase voltages are applied, then erase operation completes successfully, but stress on circuit components increases
Solution Approach 1:
The patent changes the voltage parameter distribution by applying high voltage to access lines (which can tolerate the stress) rather than to data lines and source (which are more vulnerable). This maintains successful erase operation completion while reducing harmful stress on vulnerable circuit components through selective voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates reliability concerns and simplifies the design of periphery circuitry by reducing the stress on circuit components during erase operations, leading to a more compact and efficient memory device design.
Implementation Method 1
applying an erase voltage to the channels of the memory cells (e.g., through data lines and source connections) in order to remove charges that might be stored on charge storage structures
Data Source
AI summary
Apparatus including an array of memory cells comprising a plurality of strings of series-connected memory cells, a plurality of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of series-connected memory cells, and a controller configured during an erase operation of the plurality of strings of series-connected memory cells to apply a first voltage level to a node connected to an end of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and apply a second voltage level to a particular access line of the plurality of access lines concurrently with applying the first voltage level to the node, wherein the second voltage level has a magnitude greater than the first voltage level, and is lower than the first voltage level.