Flash Memory Error Correction Based on Block Erase Count
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Solution Overview
Problem
Flash memory devices face challenges in effectively correcting errors introduced during data storage and retrieval due to the limitations of existing error correction techniques, particularly in managing error correction based on the erase count of memory blocks, which affects the reliability and efficiency of data recovery.
Innovation Solution
A method is introduced that involves maintaining an erase count for memory blocks, selecting appropriate decoders or decoder modes based on this count, and employing different error correction strategies, including using lighter-weight or heavier-weight decoders, and adjusting resource budgets and mode transitions to optimize error correction processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heavier-weight decoder is used for error correction, then error correction capability is improved, but computational resource usage increases
Solution Approach 1:
The patent applies dynamics by making the decoder selection adaptive rather than static. The system dynamically chooses between lighter-weight and heavier-weight decoders based on the erase count of memory blocks, allowing the error correction capability to adjust according to the actual reliability needs of each block.
Solution Approach 2:
The patent implements local quality by applying different decoder weights to different memory blocks based on their individual erase counts. Rather than using a uniform decoder for all blocks, the system tailors the error correction strength to the specific condition of each block, using heavier decoders only where needed.
2Reliability
If error correction is applied to all memory blocks uniformly, then data integrity is maintained, but computational resources are wasted on reliable blocks
Solution Approach 1:
The patent changes the parameter of decoder selection based on the erase count parameter of memory blocks. By using the erase count as a threshold parameter, the system determines whether to apply lighter-weight or heavier-weight decoding, optimizing the balance between data integrity and computational efficiency.
Solution Approach 2:
The patent applies partial action by using lighter-weight decoders for memory blocks with lower erase counts that require less error correction capability. This avoids the excessive application of heavy decoding resources to blocks that don't need them, while still maintaining adequate protection where required.
3Productivity
If lighter-weight decoders are used for all blocks, then computational resource usage is reduced, but error correction capability deteriorates for degraded blocks
Solution Approach 1:
The system dynamically adjusts decoder weight based on the erase count, ensuring that lighter-weight decoders are only used when appropriate (low erase count) while heavier-weight decoders are automatically selected for degraded blocks (high erase count), maintaining reliability without constant heavy resource usage.
Solution Approach 2:
The memory blocks effectively self-service their own error correction needs through the erase count mechanism. Blocks with high erase counts automatically trigger the use of heavier-weight decoders, while blocks with low erase counts use lighter-weight decoders, allowing the system to self-regulate resource allocation based on actual block conditions.
4Ease of manufacture
If traditional ECC techniques are used without considering erase count, then implementation is simple, but error correction effectiveness decreases for degraded blocks
Solution Approach 1:
The patent performs preliminary action by maintaining and tracking the erase count for each memory block in advance. This预先 information about block degradation is used to guide the subsequent selection of appropriate decoder weight, improving error correction effectiveness without requiring complex real-time analysis during the decoding process itself.
Data Source
AI summary
Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (ii) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.