Flash Memory Fail-Safe Control for Defect-Tolerant Rewriting
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Solution Overview
Problem
Existing flash memory systems face reliability issues due to defects in word lines and bit lines, which can lead to complete memory failure, as replacing blocks does not adequately address these defects, and existing EEPROM emulations struggle to handle a large number of rewrite operations reliably.
Innovation Solution
A semiconductor integrated circuit device with a flash memory and a processor that operates in both normal and fail-safe modes, where the processor commands a verify operation after rewriting, allowing for error correction and continued usage even if defects are detected, by switching to fail-safe mode when defects occur during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block replacement is used to address defects in flash memory, then local defects can be corrected, but word line and bit line defects affecting entire blocks cannot be resolved
Solution Approach 1:
The flash memory is divided into multiple blocks, with dedicated spare blocks for replacement. When a defect is detected in a data block, the system segments the problem by replacing only the affected block rather than the entire memory, while maintaining the ability to handle both local and global defects through different operational modes.
Solution Approach 2:
The system dynamically switches between normal operation mode and fail-safe mode based on the type of defect detected. In normal mode, standard block replacement is used for local defects. When word line or bit line defects are detected affecting multiple blocks, the system transitions to fail-safe mode to handle these broader defects appropriately.
2Reliability
If all usage of flash memory is stopped when a defect is discovered in normal mode, then data integrity is protected, but system availability is reduced
Solution Approach 1:
The operational mode of the flash memory system is made dynamic, allowing transition between normal mode (with strict data integrity protection stopping all usage upon defect detection) and fail-safe mode (allowing continued limited usage with error correction). This enables the system to adapt its behavior based on the severity and type of defect detected.
Solution Approach 2:
The system changes operational parameters by switching modes. In normal mode, the parameter is set to stop all usage upon defect detection. In fail-safe mode, the parameter changes to allow continued usage with error correction enabled, thus balancing data integrity with system availability based on the defect situation.
3Productivity
If ECC is used to correct single-bit errors in fail-safe mode, then continued operation is enabled, but error correction capability is limited to single-bit errors
Solution Approach 1:
The system applies partial error correction by using ECC to correct single-bit errors, which is sufficient for many common defect types. While this doesn't correct all possible error types (multi-bit errors), it provides adequate protection for the majority of cases while enabling continued operation. The fail-safe mode accepts this partial correction capability as sufficient for maintaining system availability.
Data Source
AI summary
An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode.