Flash File System Hierarchical Architecture for Mapping Efficiency
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Solution Overview
Problem
Conventional flash memory systems face inefficiencies due to the need for an erase before write process, which limits their lifetime and requires complex redesigns when changes occur in the host or flash memory interface, and storing mapping information reduces storage capacity and complicates management.
Innovation Solution
A hierarchical flash file system with a host system interface, cache memory, flash translation layer, and flash memory interface, where the cache and translation layer use the same file system as the host, allowing direct mapping of logical to physical addresses without translation, and maintaining independent mapping formats based on the host system's data unit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If mapping information is stored in the flash memory itself, then the mapping operation can be performed, but the storage capacity of the flash memory is reduced and the configuration becomes difficult to manage
Solution Approach 1:
The patent divides the flash memory system into distinct functional layers: a host system interface layer that handles mapping operations, and a flash memory layer that provides storage capacity. The mapping information is maintained in the host system rather than embedded in the flash memory device itself, separating the mapping function from the storage medium and preserving maximum storage capacity.
Solution Approach 2:
The host system acts as an intermediary between the user and the flash memory device. The host system maintains the mapping table and performs address translation, mediating between logical addresses from the user and physical addresses in the flash memory. This intermediary approach enables mapping operations while keeping the flash memory device simple and preserving its storage capacity.
2Device complexity
If the interface structure closely integrates host interface functionality with flash memory interface functionality, then the system is compact, but any change requires complete redesign of the flash memory system
Solution Approach 1:
The patent segments the interface structure into independent functional modules: a host system interface module that handles high-level protocol and mapping operations, and a flash memory interface module that handles low-level memory operations. This modular segmentation allows individual modules to be modified or replaced without requiring complete redesign of the entire system, enhancing adaptability while maintaining integrated functionality.
Solution Approach 2:
The interface structure is designed with dynamic adaptability, where the host system interface can be reconfigured to support different flash memory types, protocols, or applications without hardware changes. The logical address to physical address mapping can be dynamically adjusted based on requirements, allowing the system to adapt to changes while maintaining a compact integrated structure.
3Productivity
If logical addressing scheme is used to avoid erase operations, then write efficiency improves, but the mapping operation becomes complex requiring translation and mapping tables
Solution Approach 1:
The host system serves as an intermediary that maintains the mapping table and performs address translation between logical addresses from the user and physical addresses in the flash memory. This centralized mapping approach in the host system simplifies the flash memory device structure while enabling efficient write operations by allowing data to be written to any available physical location without requiring erase operations on previously used blocks.
Solution Approach 2:
The patent uses a mapping table that copies or replicates the logical address space in the host system, allowing the host to track logical to physical address mappings independently of the flash memory device. This copying approach enables the flash memory to operate in simple erase-write cycles while the host system handles the complexity of logical address management, improving write efficiency without requiring complex mapping operations in the flash memory device itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances flexibility and adaptability, reduces the need for complete redesigns, and improves efficiency by minimizing the erase before write operations and maintaining valid mapping information without reducing storage capacity.
Implementation Method 1
Flash memory is a transistor memory cell that is programmable through hot electron, source injection, or tunneling
Implementation Method 2
Flash memory is a transistor memory cell that is programmable through hot electron, source injection, or tunneling
Implementation Method 3
Flash memory is a transistor memory cell that is programmable through hot electron, source injection, or tunneling and erasable through the Fowler-Nordheim tunneling mechanism
Data Source
AI summary
The flash file system includes a flash memory and a subsystem interfacing between the flash memory and a host system. The subsystem includes a hierarchical structure of a host system interface, cache memory system, flash translation layer unit and a flash memory interface. The host system interface interfaces with the host system. The cache memory system has a storage capacity of a predetermined number of data units and stores data for transfer to and from the host system via the host system interface. The flash translation layer unit maps a logical address received from the host system via the host system interface and the cache memory into a physical address of the flash memory. The flash memory interface interfaces with the flash memory to transfer data to the flash memory from the cache memory system based on the physical address received from the flash translation layer unit and to transfer data from the flash memory to the cache memory system based on the physical address received from the flash translation layer unit.