Flash FPGA Switch Cell Layout for Radiation-Induced Fault Tolerance
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Solution Overview
Problem
Flash-based field-programmable gate array (FPGA) integrated circuits are vulnerable to radiation-induced errors due to heavy ions damaging silicon dioxide above or below the floating gate, causing unpredictable behavior in programmed circuits as charge traps form, leading to unintended connections or disconnections between circuit nodes.
Innovation Solution
A radiation-tolerant FPGA switching element is designed with a series-parallel combination of memory cells, where four switch transistors share a floating gate, ensuring that a radiation hit turning one transistor off does not disrupt the connection, and a hit turning one transistor on does not create an unintended connection, by maintaining all transistors in the same state, minimizing the probability of faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single flash switch with shared floating gate is used for programmable connections, then device complexity is reduced, but radiation tolerance deteriorates due to unpredictable state changes from charge trap formation
Solution Approach 1:
The patent divides a single switching function into multiple parallel flash switches (typically four), where each switch is controlled by its own independent memory transistor. This segmentation prevents a single radiation hit from causing unpredictable state changes, as the system can tolerate individual switch failures while maintaining overall connection integrity.
Solution Approach 2:
The patent assigns different functional roles to different parts of the switching element. Memory transistors are specifically designed for charge storage with high retention, while switch transistors are optimized for low-resistance conduction. This local differentiation allows each component to be optimized for its specific function, improving overall reliability without excessive complexity.
2Reliability
If multiple flash switches are used in series-parallel combination for radiation tolerance, then reliability improves, but device complexity increases
Solution Approach 1:
The patent combines multiple flash switches in a series-parallel configuration where they share common interconnects and control structures. This merging approach allows the system to achieve radiation tolerance through redundancy while minimizing the increase in device complexity by sharing resources such as word lines, bit lines, and control logic among the multiple switches.
Solution Approach 2:
The patent designs the switching element so that the same basic structure (memory transistor + switch transistor pair) serves multiple functions: individual switching control, radiation error tolerance through redundancy, and scalable integration into larger FPGA architectures. This multi-functionality reduces overall complexity by using a standardized building block approach.
3Reliability
If heavy ion radiation protection is implemented through redundant switching elements, then radiation tolerance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements redundancy in the switching element design beforehand, creating a system that can cushion against radiation-induced failures. By designing with multiple parallel switches and series-parallel configurations from the outset, the system can tolerate individual failures without compromising overall functionality, reducing the need for extremely high manufacturing precision on any single device.
Solution Approach 2:
The patent utilizes the ability to program floating gates to different charge states (programmed vs. erased) as a controllable parameter. By setting all memory transistors in a switching element to the same initial state and using voltage thresholds to control switch conduction, the system achieves reliable operation despite variations in manufacturing precision, as the binary nature of the programmed/erased states provides robust discrimination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the likelihood of false connections or disconnections, enhancing the reliability of FPGA operations in radiation environments by ensuring consistent functionality despite radiation events.
Implementation Method 1
each has a mechanism for deliberately storing electrical charge between the external gate node and the channel region of the transistor
Implementation Method 2
A heavy ion passing through the silicon dioxide either above or below the floating gate can dislocate atoms from their nominal location in the lattice structure making up the oxide
Implementation Method 3
The presence of these unwanted charge traps can allow electrons to slowly migrate from the floating gate by hopping from charge trap to charge trap
Data Source
AI summary
A radiation-tolerant flash-based FPGA switching element includes a plurality of memory cells each having a memory transistor and a switch transistor sharing a floating gate. Four such memory cells are combined such that two sets of two switch transistors are wired in series and the two sets of series-wired switch transistors are also wired in parallel. The four memory transistors associated with the series-parallel combination of switch transistors are all programmed to the same on or off state. The series combination prevents an “on” radiation-hit fault to one of the floating gates from creating a false connection and the parallel combination prevents an “off” radiation-hit fault to one of the floating gates from creating a false open circuit.