On-Chip Flash Translation Layer for Secure Page-Level Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory technologies face inefficiencies in updating data at the same location while preserving existing data, leading to multiplied operations and security issues due to restricted access granularity and lack of secure data protection.
Innovation Solution
Implementing flash translation layer (FTL) logic on the flash memory integrated circuit to manage logical-to-physical address mapping, verify access tokens, and perform secure data operations, allowing flexible access granularity and efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional flash memory operations are used to update data at the same location, then data can be stored, but multiple operations are required and old data must be preserved through complex read-erase-program sequences
Solution Approach 1:
The patent introduces an on-chip FTL (Flash Translation Layer) as an intermediary between the host and flash memory array. This FTL manages logical-to-physical address mapping and handles update operations transparently, eliminating the need for complex host-side read-erase-program sequences. The FTL absorbs the operational complexity and presents a simplified interface to the host system.
Solution Approach 2:
The patent implements a copy-back mechanism where updated data is first written to a new physical location and then the old physical location is updated in a subsequent operation. This copying approach allows incremental updates without requiring the entire sector to be erased first, thereby simplifying the update sequence and improving efficiency.
2Reliability
If fine-grained access control is implemented at the host level, then security can be enforced, but access granularity is restricted to entire sectors rather than individual pages
Solution Approach 1:
The patent segments the flash memory address space into pages rather than treating entire sectors as access units. The on-chip FTL maintains page-level logical-to-physical mappings and implements access control decisions at the page level, allowing fine-grained security policies where different applications can access specific pages within a sector while other pages remain protected.
Solution Approach 2:
The on-chip FTL acts as a security intermediary that enforces access control policies between the host and flash memory. It verifies access tokens and enforces security rules at the page level, providing both fine-grained access control and security enforcement without requiring the host to manage complex sector-level access control.
3Reliability
If multiple operations are performed to update the same page while preserving old data, then data integrity is maintained, but the number of operations increases and P/E cycles are consumed inefficiently
Solution Approach 1:
The patent implements a copy-back update mechanism where new data is written to a new physical page location first, and the logical-to-physical mapping is updated to point to the new location. The old physical page is then invalidated and can be reused later through garbage collection. This approach maintains data integrity while reducing the number of immediate operations required compared to traditional read-erase-program sequences.
Solution Approach 2:
The FTL performs preliminary actions by pre-allocating new physical locations for updated data and updating logical-to-physical mappings before the old data needs to be reclaimed. This preliminary action allows updates to proceed without immediately triggering erase operations, deferring P/E cycle consumption until later when garbage collection can batch multiple invalidations together.
Data Source
AI summary
An integrated circuit includes an array of flash memory and flash translation layer (FTL) logic coupled to the array and to be coupled to a host device. The FTL logic is configured to receive, from the host device, a write command comprising a first logical address, user data, and an access token and translate the first logical address to a first physical address of the array. In an embodiment, the first physical address has already been programmed. The FTL logic is further to verify the access token as being associated with the first logical address, cause the user data to be programmed to a second physical address of the array, and update at least one logical-to-physical (L2P) mapping table with the second physical address as being mapped to the first logical address.