Flash Fuse Cell Arrays for Redundancy and DC Level Control
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Solution Overview
Problem
Conventional flash memory devices face challenges in efficiently managing defective cells, manufacturing variability, and controlling DC levels due to the limitations of metal fuses, which can be unreliable and require complex laser-based programming.
Innovation Solution
The implementation of a flash memory device with a fuse cell array that includes multiple fusing circuits formed with flash fuse cells, allowing for simultaneous programming, erasure, and address management, along with a fuse sense amplifying circuit to read data from shared bit lines, replacing traditional metal fuses with flash fuse cells that can be easily reprogrammed and erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal fuses are used for fuse circuits, then the device structure is simple, but the reliability is poor and laser-based programming is required
Solution Approach 1:
The patent replaces metal fuses (mechanical/physical cutting system) with flash fuse cells (electronic programming system). This substitution eliminates the need for laser-based mechanical cutting and enables reliable electrical programming and erasing of fuse circuits, directly resolving the contradiction between reliability and programming complexity.
Solution Approach 2:
The patent changes the state parameter of the fuse circuit from irreversible metal fuse cutting to reversible flash memory programming. By using flash fuse cells, the fuse state can be electrically programmed and erased multiple times, improving reliability while simplifying the programming process through electrical control rather than laser processing.
2Adaptability or versatility
If multiple fuse circuits are implemented with separate structures, then each circuit can be independently controlled, but the device area increases
Solution Approach 1:
The patent merges multiple fuse circuits (first, second, and third fuse circuits) into a single integrated flash fuse cell array. By sharing common bit lines and sense amplifying circuits among multiple fuse circuits, the patent achieves independent control of each fuse circuit while significantly reducing the overall device area compared to separate implementations.
Solution Approach 2:
The patent implements multi-functionality by having shared bit lines and sense amplifying circuits serve multiple fuse circuits simultaneously. The same bit lines and sense amplifiers are used across different fuse circuits, enabling one structure to perform multiple functions and reducing redundant components, thus decreasing device area while maintaining independent controllability.
3Measurement precision
If dummy fuse cells are added to compensate for leakage currents, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
The patent implements self-service by designing the flash fuse cell structure to inherently compensate for leakage currents through its own operational characteristics. The flash fuse cells automatically adjust for leakage effects during programming and sensing operations, eliminating the need for external dummy fuse cells and the associated complexity, while maintaining measurement precision.
Data Source
AI summary
A flash memory device includes a flash cell array, a first flash fuse cell fusing circuit, a second flash fuse cell fusing circuit, a third flash fuse cell fusing circuit and a plurality of fuse sense amplifying circuits. The first, second and third flash fuse cell fusing circuits all share bit lines with a flash cell array and have flash fuse cells. The first flash fuse cell fusing circuit may be used to control a connection between the flash cell array and an external logic circuit. The second flash fuse cell fusing circuit may be used to change an address of a defective cell into an address of a redundancy cell. The third flash fuse cell fusing circuit may be used to control a DC level for adjusting a reference value used in a manufacturing process of the flash memory device. The fuse sense amplifying circuits are coupled to the bit lines to read data from the bit lines, respectively.