Flash Gate Air Gap for Flash Memory Charge Trapping
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Solution Overview
Problem
Current selective dry isotropic silicon oxide etch processes for semiconductor substrates lack the necessary versatility to effectively remove dummy silicon oxide without damaging the structural silicon oxide, leading to trapped charges and premature failure in flash memory devices.
Innovation Solution
The introduction of a remote plasma etch process using a fluorine-containing precursor and an ion suppressor plate to selectively remove doped silicon oxide, creating an air gap that reduces charge accumulation and increases the lifespan of flash memory devices by ensuring low electron temperatures and minimizing ion-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional selective dry isotropic silicon oxide etch processes are used, then material removal is achieved, but the process lacks versatility to selectively remove dummy silicon oxide without damaging structural silicon oxide
Solution Approach 1:
The patent applies local quality by doping the dummy gate silicon oxide with phosphorus to create a distinct material property (higher etch rate) compared to the undoped structural silicon oxide. This localized doping enables selective removal of dummy gates while preserving structural oxides during the isotropic etch process, resolving the contradiction between etch versatility and device reliability
Solution Approach 2:
The patent changes the chemical composition parameter of the dummy gate silicon oxide by introducing phosphorus doping. This parameter change creates a significant etch rate differential that allows the etch process to selectively remove dummy gates while leaving structural silicon oxide intact, thereby achieving both process versatility and device reliability
2Ease of operation
If silicon oxide is used as a dielectric barrier, then electron passage is enabled, but trapped charges accumulate leading to premature failure
Solution Approach 1:
The patent extracts the problematic silicon oxide dielectric material from the flash memory cell structure and replaces it with an air gap. This removal eliminates the charge trapping issue inherent to silicon oxide while preserving the essential function of electrical isolation and electron passage capability through the floating gate, thereby improving device reliability without sacrificing operational functionality
3Productivity
If repeated writings are performed, then data storage is achieved, but charge trapping occurs and alters operating voltages
Solution Approach 1:
The patent removes the silicon oxide dielectric layer that causes charge trapping during repeated write operations. By replacing it with an air gap, the structure eliminates the source of trapped charges that would otherwise accumulate and shift operating voltages, enabling sustained high-speed data writing without degradation of voltage stability
4Productivity
If doped silicon oxide is used for dummy gate, then etch rate is increased, but selectivity control becomes more challenging
Solution Approach 1:
The patent applies local quality by doping only the dummy gate silicon oxide with phosphorus while leaving the structural silicon oxide undoped. This creates a clear material distinction that simplifies selectivity control - the etch process naturally targets the doped dummy gates first due to their higher etch rate, providing self-guided selectivity that reduces manufacturing complexity while maintaining precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the etch selectivity and reduces the tendency for charge trapping, thereby extending the lifespan of flash memory devices and preventing self-induced leakage current, while maintaining the integrity of the structural silicon oxide.
Implementation Method 1
A fluorine-containing precursor is excited in a remote plasma to form plasma effluents
Implementation Method 2
plasma effluents are flowed into the substrate processing region where they selectively etch the dummy gate
Implementation Method 3
plasma effluents are passed through an ion suppressor plate into a substrate processing region where they selectively etch the dummy gate. The etch selectivity of the dummy gate (doped silicon oxide) relative to the structural silicon oxide is enabled by inclusion of an ion suppressor plate to ensure a low electron temperature in the substrate processing region
Data Source
AI summary
Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.