Ground Selection Transistor Structure for Common Source Line Isolation
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Solution Overview
Problem
The complexity of manufacturing flash memory devices makes it difficult to individually control various lines such as string selection and ground selection lines, leading to reduced reliability and performance, as well as increased power consumption.
Innovation Solution
The memory device incorporates a structure where ground selection transistors are connected to ground selection lines in units of rows, allowing individual control of each cell string, with threshold voltages set to ensure only the selected cell string is electrically connected to the common source line, while unselected strings are isolated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ground selection transistors are controlled individually in units of cell string, then reliability and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The ground selection transistors are divided into multiple groups, with each group associated with a specific cell string. Each group can be independently controlled through separate ground selection lines, enabling individual control of ground selection for each cell string while maintaining a structured, scalable architecture that manages manufacturing complexity.
Solution Approach 2:
The patent introduces multiple ground selection lines extending in a direction perpendicular to the bit lines, creating a vertical or stacked dimensional arrangement. This dimensional change allows individual control of ground selection transistors for each cell string without increasing lateral manufacturing complexity, as the control lines are organized in a vertical hierarchy rather than horizontal expansion.
2Productivity
If ground selection transistors are controlled individually in units of cell string, then performance is improved, but power consumption increases
Solution Approach 1:
By segmenting the ground selection control into multiple independent lines, the system can activate only the ground selection transistors needed for the currently selected cell string. This selective activation reduces the number of simultaneously active transistors, thereby lowering overall power consumption while maintaining high performance for the selected string.
Solution Approach 2:
The control mechanism periodically activates specific ground selection lines based on which cell string is currently being accessed. Instead of maintaining all ground selection transistors in an active state, the system dynamically switches activation between different ground selection lines corresponding to different cell strings, reducing average power consumption while ensuring high performance during active operations.
3Reliability
If multiple ground selection lines are used for individual cell string control, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent resolves the complexity issue by organizing multiple ground selection lines in a vertical dimension perpendicular to the bit lines. This stacked arrangement allows individual control of ground selection transistors for each cell string while maintaining a compact, systematic structure that is easier to manufacture and less complex than lateral expansion approaches.
Solution Approach 2:
Each ground selection line serves multiple functions: it controls the ground selection transistors for its associated cell string, provides a reference for voltage levels, and can be selectively activated based on read or program operations. This multi-functionality reduces the need for additional dedicated control structures, thereby managing device complexity while maintaining high reliability.
Data Source
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AI summary
An example memory device includes a substrate, and a first cell string and a second cell string on the substrate between a first bit line and a common source line. The first cell string includes a first string selection transistor connected to a first string selection line and first and third ground selection transistors connected to first and second ground selection lines, respectively. The second cell string includes a second string selection transistor connected to a second string selection line and second and fourth ground selection transistors connected to the first and second ground selection lines, respectively. When the first cell string is a selected cell string, in the second cell string, the second and fourth ground selection transistors are turned off, and at least one ground selection transistor between the second and fourth ground selection transistors is turned on.