Flash Interface Sudden Power Off Recovery Using pSLC Blocks
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Solution Overview
Problem
Sudden power off events can result in data loss in NAND flash memory devices due to their serial access nature, which complicates the recovery of dynamic random access memory (DRAM) data.
Innovation Solution
A method and apparatus that utilize pseudo single-level cell (pSLC) blocks in a single-level cell mode across multiple channels to rapidly program and then erase data from these blocks, enabling efficient recovery of DRAM data during a sudden power off event, employing interleave page programming and Logical-to-Physical (L2P) table updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is used for storage, then storage capacity is improved, but data loss occurs during sudden power off due to serial access nature
Solution Approach 1:
The flash memory is divided into multiple channels, each channel handling independent data transfer operations. This segmentation allows parallel processing of data across multiple channels, improving both throughput and reliability during sudden power off events by distributing the data protection burden across multiple independent pathways.
Solution Approach 2:
The system performs preliminary actions by detecting sudden power off conditions and initiating recovery procedures before complete data loss occurs. The method monitors power status and prepares recovery mechanisms in advance, allowing the system to switch to recovery mode and protect critical data before the power interruption causes irreversible damage.
2Speed
If DRAM is used for caching, then access speed is improved, but data loss occurs after sudden power off
Solution Approach 1:
The system uses an intermediary mechanism between DRAM and flash memory to prevent data loss. When sudden power off is detected, the recovery method acts as an intermediary process that retrieves data from flash memory channels and restores it to DRAM, bridging the gap between non-volatile and volatile storage during the transition period.
Solution Approach 2:
The system implements feedback by continuously monitoring the state of DRAM and flash memory, detecting power off conditions, and triggering appropriate recovery actions. The feedback loop ensures that data integrity is maintained by comparing expected data states with actual states and initiating corrective recovery operations when discrepancies are detected.
3Device complexity
If serial access mode is used in NAND flash, then device complexity is reduced, but data transfer speed decreases
Solution Approach 1:
The system transitions from one-dimensional serial access to multi-dimensional parallel access by utilizing multiple independent channels simultaneously. This dimensional change allows data to flow through multiple pathways at once, dramatically increasing throughput while maintaining the simplicity of individual channel operations. Each channel operates independently in parallel, achieving high-speed transfer without complicating the fundamental access mechanism.
Data Source
AI summary
The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.