Flash Memory Interrupt Thresholds for Low-Power Management

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Solution Overview

Problem

In flash memory devices, interrupts generated by low-power mode host devices to inform the host of exception events cause unnecessary power consumption, as they transition out of low-power mode to service these events, draining critically low system power.

Innovation Solution

A host device sets an interrupt level in a flash memory device's register, indicating permissible sources of interrupts based on background operation status, postponing lower-priority operations and adding them to a wait queue, and selectively suspending or resuming operations based on power conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the flash memory device generates interrupts to inform the host device of exception events during low-power mode, then the host device can service exception events promptly, but the host device transitions out of low-power mode causing increased power consumption

Engineering Contradiction:
Improveexception event handlingVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by introducing an interrupt level parameter that thresholds exception events into different priority levels. The host device configures the flash memory device to generate interrupts only when exception events exceed a specified interrupt level threshold. This parameter-based filtering allows the system to maintain reliable exception handling for critical events while suppressing interrupts for lower-priority events during low-power mode, thereby reducing unnecessary wake-ups and power consumption.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the host device allows all background operation statuses to trigger interrupts, then all exception events are serviced, but power is drained during low-power mode due to unnecessary transitions

Engineering Contradiction:
Improveexception event coverageVSAvoidsystem power
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements parameter changes by configuring an interrupt level parameter that selectively enables or disables interrupt generation based on exception event priority. The host device sets this parameter to allow interrupts only for high-priority exception events while suppressing lower-priority events during low-power operation. This selective parameter configuration maintains comprehensive exception event coverage for critical operations while preventing energy loss from unnecessary interrupt handling and mode transitions.

Inventive Principle:
Principle #35Parameter changes

3Speed

If the host device transitions out of low-power mode to service interrupts, then exception events are handled in real-time, but critical power is consumed that could be used for more important system functions

Engineering Contradiction:
Improveexception event response timeVSAvoidavailable power for critical functions
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by introducing and configuring an interrupt level parameter that filters exception events by priority. During low-power mode, the host device sets this parameter to a high threshold, allowing interrupts only for the most critical exception events. This ensures that real-time response is maintained for urgent matters while preventing power consumption for less critical events. The parameter dynamically adjusts interrupt sensitivity based on system power conditions, optimizing the balance between response speed and power conservation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12461670B2Enhanced power management of flash memory device
Publication Date: 2025.11.04 QUALCOMM INC
  • US12461670B2 patent drawing
  • US12461670B2 patent drawing
  • US12461670B2 patent drawing

AI summary

A device includes a flash interface configured to be coupled to a flash memory device. The device also includes a host controller configured to select an interrupt level that indicates a threshold background operation status of a set of background operation statuses. The host controller is also configured to write the selected interrupt level to a register at the flash memory device to indicate, to the flash memory device, which of the set of background operation statuses are permissible sources of an interrupt from the flash memory device to the host controller.