Flash Controller I/O Termination Circuit for Multi-Standard Signal Matching
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Solution Overview
Problem
Conventional input/output circuits in flash memory controllers fail to meet the evolving specification standards, requiring a more flexible and adjustable signal matching solution for different flash memory products and standards.
Innovation Solution
The implementation of a configurable input/output interface circuit within a flash memory controller, featuring a transmission and on-die termination circuit that can operate as either an output driving stage or an input on-die termination stage, controlled by a processor circuit to provide matching termination resistance for various signal standards, such as NV-DDR3 and NV-LPDDR4, through control signals TE, TR_DU, TR_DD, DU, and DD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional input/output circuit with fixed signal matching resistance is used, then the circuit structure is simple, but it cannot meet the requirements of different flash memory specification standards
Solution Approach 1:
The patent implements a dynamic I/O interface circuit that can switch between output driving mode and input on-die termination mode based on control signals. The transmission and on-die termination circuit is configured to operate as an output driving stage circuit when receiving a first control signal, and as an input on-die termination stage circuit when receiving a second control signal, enabling adaptation to different flash memory standards without increasing physical circuit complexity
Solution Approach 2:
The patent creates a universal I/O interface circuit that serves multiple functions: it can act as both an output driving stage circuit and an input on-die termination stage circuit depending on the control signal received. This multi-functional design allows a single circuit structure to meet requirements of different flash memory specification standards, resolving the contradiction between adaptability and complexity
2Reliability
If a fixed signal matching resistance is provided, then the circuit design is simple, but signal quality and reflection control are insufficient for evolving standards
Solution Approach 1:
The patent employs dynamic control of the transmission and on-die termination circuit through control signals from the processor circuit. When operating as an output driving stage, the circuit provides appropriate driving strength; when operating as an input on-die termination stage, it generates and provides a matching termination resistance for the I/O signal port. This dynamic switching enables reliable signal quality and reflection control across different standards without requiring multiple fixed circuit configurations
Solution Approach 2:
The patent changes the operational parameters of the transmission and on-die termination circuit based on control signals. The circuit can adjust its termination resistance values and driving characteristics dynamically, allowing it to provide optimal signal matching for different flash memory standards. This parameter-based adaptability improves signal quality and reflection control without increasing physical circuit complexity
Data Source
AI summary
An input/output (I/O) interface circuit, disposed within a flash memory controller and to be coupled to a flash memory externally coupled to the flash memory controller through an I/O signal port of the flash memory controller, includes a transmission and on-die termination circuit operating as either an output driving stage circuit or an input on-die termination stage circuit. The transmission and on-die termination circuit operates as the output driving stage circuit to transfer and drive a transmission signal, sent from the processor circuit of the flash memory controller, to the flash memory through the I/O signal port. The transmission and on-die termination circuit operates as the input on-die termination stage circuit for generating and providing a matching termination resistance for the I/O signal port.