Flash Memory LDPC Decoding With Inverted Data Flow
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Solution Overview
Problem
Conventional bit-flipping LDPC decoders in flash memory systems experience high power consumption due to a high toggle rate on data lines, primarily because of a large proportion of '1's in the codeword data during the decoding phase.
Innovation Solution
The proposed memory controller and method alter the data-control flow between the variable-node and check-node circuits during decoding, reducing the ratio of '1's in the codeword accessed by the variable-node unit, thereby lowering the toggle rate on data lines and eliminating the need to access channel values from memory during decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional bit-flipping LDPC decoding is used with traditional data flow between variable-node and check-node circuits, then decoding functionality is achieved, but power consumption increases due to high toggle rate on data lines
Solution Approach 1:
The patent inverts the traditional LDPC decoding data flow by having check-node circuits send codeword data to variable-node circuits instead of the conventional direction. This inversion changes the sequence of operations and allows variable-node circuits to perform bit-flipping on received codeword data, reducing the toggle rate on data lines and thereby lowering power consumption while maintaining decoding functionality
Solution Approach 2:
The patent changes the operational parameters of the LDPC decoding process by modifying when and how codeword data is accessed and processed. By altering the data flow sequence and having variable-node circuits operate on codeword data received from check-node circuits, the patent reduces the frequency of data line toggles, thus changing the energy consumption parameter favorably
2Use of energy by moving object
If channel values are accessed from memory during each decoding iteration, then decoding accuracy is maintained, but power consumption increases due to repeated memory access operations
Solution Approach 1:
The patent extracts the channel value access operation from the iterative decoding process. Instead of accessing channel values from memory during each decoding iteration, the channel values are read once before decoding and stored in registers. This extraction eliminates repeated memory access operations, significantly reducing power consumption while maintaining decoding accuracy through register-based operations
Solution Approach 2:
The patent performs the channel value read operation in advance before the iterative decoding process begins. By preliminarily loading channel values into registers, the system avoids repeated memory access during decoding iterations, thereby reducing power consumption while ensuring decoding accuracy is maintained through the use of pre-loaded values
Data Source
AI summary
A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During each LDPC decoding iterative operation in the decoding phase: the check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit is configured to: determine a syndrome weight according to the syndrome from the check-node circuit; obtain a previous codeword from a variable-node memory without obtaining a channel value from a channel-value memory; perform bit-flipping on one or more codeword bits in the previous codeword according to the calculated syndrome weight to generate an updated codeword; and subtract the previous codeword from the updated codeword to obtain the codeword difference.