Flash Memory LDPC Encoding with Auxiliary Data in Dependent Bits

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Solution Overview

Problem

In flash memory systems, non-full-rank parity check matrices in Low-Density Parity Check (LDPC) encoders generate parity codes with dependent bits that lack error correction properties, leading to wastage of memory space.

Innovation Solution

An encoding circuit that utilizes the addresses of dependent bits to store auxiliary data, generating an adjusted parity code by replacing dependent bits with auxiliary data, thereby optimizing memory usage and ensuring error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a non-full-rank parity check matrix is used in the LDPC encoder, then the encoding process can be simplified, but the generated parity code contains dependent bits that waste memory space and lack error correction properties

Engineering Contradiction:

Improveencoding process complexityVSAvoidmemory space utilization

Core Design Contradiction:

Device complexityVSLoss of substance

Solution Approach 1:

The patent extracts the dependent bits from the parity code and replaces them with auxiliary data. The auxiliary data generating circuit creates checksum data from the data chunks, and the compensating circuit replaces the dependent bits in the parity code with this auxiliary data, thereby removing the useless dependent bits and utilizing memory space effectively

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes the parity code serve multiple functions: it maintains error correction capabilities for the data chunks while simultaneously storing auxiliary data (such as checksum data) in the positions of previously dependent bits. This multi-functionality resolves the contradiction by making the memory space useful for both error correction and data integrity verification

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Stability of the object's composition

If dependent bits are retained in the parity code, then the parity check matrix structure is maintained, but error correction capability is reduced and memory space is wasted

Engineering Contradiction:

Improveparity check matrix structureVSAvoiderror correction capability

Core Design Contradiction:

Stability of the object's compositionVSReliability

Solution Approach 1:

The patent applies local quality by treating different parts of the parity code differently. The independent bits in the parity code maintain their error correction function, while the dependent bit positions are repurposed to store auxiliary data. This localized differentiation allows the system to maintain the overall parity check matrix structure while improving reliability through functional specialization

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10938417B2Flash memory controller and encoding circuit and decoding circuit within flash memory controller

Publication Date: 2021.03.02 SILICON MOTION INC

AI summary

The present invention provides an encoding circuit of a flash memory controller, wherein the encoding circuit includes an auxiliary data generating circuit and an encoder. In the operations of the encoding circuit, the auxiliary data generating circuit is configured to receive a plurality of data chunks to generate auxiliary data corresponding to the data chunks. The encoder is configured to encode the data blocks to generate parity codes according to a parity check matrix, and to use the auxiliary data to replace a portion of the parity codes to generate adjusted parity codes, wherein the data chunks and the adjusted parity codes are written into a flash.