Flash Memory LDPC Controller with Low-Toggle Decoding Flow
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Solution Overview
Problem
Conventional bit-flipping LDPC decoders experience high power consumption due to a high toggle rate on data lines, primarily because of the large number of 1's in the codeword data, which leads to increased power consumption during the decoding phase in flash memory systems.
Innovation Solution
A memory controller and method that alternate the data-control flow between the variable-node and check-node circuits during decoding, reducing the ratio of 1's in the codeword accessed and minimizing the number of read and write operations to the variable-node memory, thereby reducing power consumption by not accessing channel values during the decoding phase and using update flags to determine data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit-flipping LDPC decoding is performed with high number of 1's in codeword data, then decoding functionality is achieved, but power consumption increases due to high toggle rate on data lines
Solution Approach 1:
The patent extracts and processes only the error pattern (difference between current and previous codewords) rather than the entire codeword. By taking out only the changed bits and their positions, the system maintains decoding functionality while significantly reducing the number of 1's in processed data, thereby reducing toggle rate and power consumption on data lines
Solution Approach 2:
The patent changes the parameter being processed from the complete codeword to the error pattern (difference codeword). This parameter transformation reduces the density of 1's in the data being transferred and processed during iterative decoding operations, directly addressing the power consumption issue caused by high toggle rates
2Reliability
If channel value is accessed during decoding phase, then decoding accuracy is maintained, but power consumption increases due to additional memory access operations
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing the error pattern before the decoding phase begins. By preparing the difference codeword in advance and storing it in memory, the system eliminates the need to access channel values during the actual decoding iterations, reducing power consumption while maintaining decoding accuracy through the pre-prepared error information
3Reliability
If frequent read and write operations are performed on variable-node memory, then decoding convergence is achieved, but power consumption increases due to high operation count
Solution Approach 1:
The patent extracts only the essential error pattern information needed for decoding convergence rather than performing full codeword read/write operations. By storing and processing only the difference codeword (error pattern) in variable-node memory, the system achieves decoding convergence with significantly fewer memory operations, directly reducing power consumption associated with frequent read/write cycles
Data Source
AI summary
A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.