Flash LED Driver Circuit With Dynamic Voltage Headroom Adjustment
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Solution Overview
Problem
Conventional flash LED drivers operate with a constant voltage headroom (VHR), leading to inefficient energy use and increased manufacturing costs due to the need for larger field-effect transistors to reduce on-resistance, which is undesirable in size-reduction efforts and consumer applications.
Innovation Solution
A dynamic VHR system that adjusts voltage headroom based on a programmed brightness for LEDs, using a processing element to generate a partition control signal that switches transistors into or out of the signal path, reducing VHR without increasing transistor size by modifying the number of transistors active, rather than decreasing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant voltage headroom (VHR) is used in flash LED drivers, then the circuit operation is simplified, but energy efficiency deteriorates and manufacturing costs increase due to larger transistor requirements
Solution Approach 1:
The patent implements dynamic voltage headroom adjustment by switching between different transistor configurations (single transistor vs. parallel transistor pairs) based on the required current level. This dynamic reconfiguration allows the circuit to optimize its VHR in real-time, improving energy efficiency while maintaining operational simplicity through automated control.
Solution Approach 2:
The system changes the voltage headroom parameter dynamically by adjusting the number of active transistors based on the digital input signal range. When the signal is in the first value range, a first VHR is applied; when in the second value range, a second VHR is applied. This parameter adaptation resolves the contradiction between simplified operation and energy efficiency.
2Loss of energy
If larger field-effect transistors are used to reduce on-resistance, then energy efficiency improves, but device area increases which is undesirable in size-reduction efforts
Solution Approach 1:
The patent segments the transistor function by using multiple smaller transistors that can be switched in parallel rather than relying on a single large transistor. This segmentation allows the circuit to achieve low on-resistance when needed (by activating parallel transistors) while maintaining small device area when the full current capacity is not required.
Solution Approach 2:
The system dynamically switches between single-transistor and parallel-transistor configurations based on the operating conditions. This dynamic approach allows the circuit to use larger effective transistor area only when high current is needed, resolving the contradiction between reducing on-resistance loss and minimizing device area.
3Loss of energy
If the number of transistors is increased to reduce VHR, then energy efficiency improves, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent segments the transistor bank into manageable pairs that can be selectively activated. This segmentation allows the system to use multiple transistors to reduce VHR when needed, while keeping the overall device complexity manageable through systematic organization and automated switching based on the digital input signal.
Data Source
AI summary
Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.