Flash Storage Error Correction Across Logical Addresses
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Solution Overview
Problem
Traditional error correction techniques in flash memory devices, such as ECC and RAIN, can be inadequate in protecting data from corruption, especially when an entire block malfunctions, and may introduce complexity or inefficiency.
Innovation Solution
An extended error correction technique is implemented, which provides an additional level of error correction information orthogonal to primary error correction, spread across logical block addresses, allowing for flexible error protection by computing secondary error correction data based on logical addresses and storing it accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction techniques (ECC and RAIN) are used in flash memory devices, then data protection is provided, but the protection is inadequate when entire blocks malfunction and the system complexity increases
Solution Approach 1:
The patent transitions from physical-domain error correction (ECC/RAIN operating on physical blocks) to logical-domain error correction (operating on logical block addresses). This dimensional shift allows error correction to function independently of physical block failures, providing broader protection without increasing physical complexity. The logical address mapping creates an abstract layer that decouples error correction from physical constraints.
Solution Approach 2:
The patent introduces logical block addresses as an intermediary layer between the host and physical storage blocks. This intermediary enables error correction operations to be performed on logical addresses rather than directly on physical blocks, providing flexibility to handle physical block failures while maintaining simple error correction mechanisms at the logical level.
2Reliability
If extended error correction is implemented across logical block addresses, then data integrity is enhanced, but computation and storage overhead increases
Solution Approach 1:
The patent makes the error correction system universal by operating on logical block addresses rather than being tied to specific physical blocks. This multi-functionality allows the same error correction mechanism to protect data regardless of which physical blocks are used, eliminating the need for separate error correction schemes for different physical configurations and reducing overall error correction data requirements.
Solution Approach 2:
The patent changes the fundamental parameter of error correction from physical block addresses to logical block addresses. This parameter transformation allows error correction to be performed in the logical domain where addresses can be freely mapped and reassigned, reducing the constraints that would otherwise require additional error correction data for physical block management.
Data Source
AI summary
Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.