Flash Storage Mapping Verification with Metadata and Block Migration
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Solution Overview
Problem
Nonvolatile storage systems face challenges in maintaining the integrity of logical-physical address maps while minimizing resource consumption, particularly in processes involving read-back operations with small-capacity working memories.
Innovation Solution
A storage system with first and second memory blocks, utilizing a controller to perform operations such as programming, movement, and verification to maintain the integrity of logical-physical address maps, including a valid or blind data copy scheme to manage data between single-level cell (SLC) and quadruple-level cell (QLC) blocks, and using metadata to store necessary physical address information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read-back operation is performed to maintain integrity of the logical-physical address map, then mapping integrity is improved, but working memory resource consumption increases
Solution Approach 1:
The patent segments the address map verification process into multiple parts: it divides the address space into ranges, processes mappings in batches rather than all at once, and separates the verification of physical addresses from logical addresses. This segmentation allows the system to maintain mapping integrity while using smaller working memory resources at any given time.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing certain address mapping information in the address translation cache before it is needed for verification. It also pre-organizes the address ranges and prepares the verification data structures in advance, reducing the working memory burden during the actual read-back operation.
2Adaptability or versatility
If data is moved between memory blocks, then storage flexibility is improved, but risk of mapping errors increases
Solution Approach 1:
The patent implements feedback mechanisms through verification operations that check the accuracy of address mappings after data movement. The system reads back the moved data, verifies that the logical-to-physical address mappings are correct, and uses this feedback to detect and correct any mapping errors that occurred during the data transfer process.
Solution Approach 2:
The patent prepares cushioning measures in advance by maintaining redundant address mapping information in the address translation cache and implementing error detection codes. These preparatory measures act as a buffer that can compensate for or detect mapping errors if they occur during data movement operations.
Data Source
AI summary
A storage device programs a requested data unit into a second memory block by programming the requested data unit into the first memory block corresponding to a logical address included in the request and updating a mapping relationship between a physical address indicating a first memory block and the logical address and moving the programmed data unit to the second memory block. A controller records the logical address and the physical address in a meta data unit corresponding to the requested data unit and verifies integrity of the mapping relationship for the moved data unit.


