Flash Memory Address Mapping Cache for Large-Capacity Storage
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Solution Overview
Problem
Conventional flash memory controllers are limited by the size of their cache buffer space, which restricts their ability to support memory address spaces larger than 4 TB due to circuit costs and internal storage capacity constraints.
Innovation Solution
Implementing a multi-layer address mapping method that divides address mapping relations into segments, caching some in the controller's buffer and others in the flash memory, allowing dynamic configuration of cache space to support larger memory spaces like 8 TB, 16 TB, or more, while maintaining access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all address mapping relations are stored in cache buffer space within flash memory controller, then access speed is improved, but device complexity and circuit cost increase
Solution Approach 1:
The patent divides the address mapping relations into two segments: frequently accessed mappings are stored in the cache buffer space within the flash memory controller for fast access, while less frequently accessed mappings are stored in the flash memory itself. This segmentation allows the system to maintain high access speed for common operations without requiring the controller to handle the entire address space, thereby reducing circuit complexity and cost.
2Adaptability or versatility
If cache buffer space size is increased to support larger physical memory address space, then adaptability is improved, but device complexity and circuit cost increase
Solution Approach 1:
The patent implements a dynamic cache management system where the cache buffer space is allocated and managed flexibly based on actual access patterns. The controller dynamically determines which address mapping relations to cache and which to store in flash memory, allowing the system to adapt to different physical memory address spaces (4TB, 8TB, 16TB, or above) without requiring a proportional increase in cache buffer hardware. This dynamic approach enables high adaptability while keeping circuit costs manageable.
3Speed
If all address mapping data is kept resident in flash memory controller, then access speed is improved, but loss of substance occurs due to limited cache buffer space
Solution Approach 1:
The patent introduces the flash memory as an intermediary storage layer between the host device and the ultimate data storage. When the cache buffer space is full, the controller selectively evicts less frequently accessed address mapping relations from the cache to the flash memory. This intermediary approach allows the system to maintain a small, efficient cache while using the flash memory to store the complete address mapping database, thereby preventing data loss due to cache limitations while maintaining fast access speeds for commonly used mappings.
Data Source
AI summary
A flash memory controller includes a specific buffer and a processor. The specific buffer allocates a cache space. The processor receives a specific host address sent from the host device, reads and loads a corresponding address pointer mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer linker, determines a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reads and loads a corresponding address mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer corresponding to the specific host address, and finds a specific flash memory address from the corresponding address mapping table according to the specific host address to perform an access operation in response to the found specific flash memory address.