Flash Memory Mapping Table Update Sub-Intervals
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Solution Overview
Problem
Existing Flash memory control methods face challenges in maintaining timely responses to host commands due to the time-consuming process of updating the logical-to-physical address mapping table for entire buffer blocks, which can lead to postponed command execution.
Innovation Solution
Implementing a controller that updates the logical-to-physical address mapping table in separated update sub-intervals for a master buffer block, allowing for continuous response to host commands without waiting for the completion of the entire buffer block update, and utilizing a slave buffer block to buffer data during these intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the logical-to-physical address mapping table is updated for the entire buffer block at once, then the mapping relationship is accurately maintained, but the command response time is significantly delayed
Solution Approach 1:
The patent divides the buffer block into multiple segments and updates the mapping table for each segment independently in separate update sub-intervals. This segmentation allows the mapping table update to be performed partially without blocking the entire buffer block, thereby maintaining mapping accuracy while reducing command response time delay.
Solution Approach 2:
The patent implements dynamic update intervals where the controller can switch between different buffer blocks (master buffer block and slave buffer block) during the mapping table update process. This dynamic approach allows continuous operation of the Flash memory device while updating mapping relationships, resolving the contradiction between accuracy and response time.
2Reliability
If the mapping table update is performed continuously without interruption, then the mapping relationship is fully updated, but the host commands cannot be responded to in a timely manner
Solution Approach 1:
The mapping table update process is segmented into multiple update sub-intervals, and the buffer block is divided into master and slave portions. During each update sub-interval, only the mapping table for the current buffer block is updated while other operations can proceed, maintaining both update completeness and command processing throughput.
Solution Approach 2:
The patent introduces a slave buffer block as an intermediary to handle commands during the master buffer block's mapping table update. This intermediary mechanism allows the system to maintain productivity by processing commands in the slave buffer while the master buffer undergoes mapping table updates, ensuring both completeness and throughput.
3Reliability
If the entire buffer block mapping table is updated before responding to host commands, then the mapping accuracy is ensured, but the operational fluency is reduced
Solution Approach 1:
The patent implements a dynamic update mechanism where the mapping table is updated in interleaved fashion with command processing. The controller can switch between master and slave buffer blocks during updates, ensuring mapping accuracy is maintained while operational fluency is preserved through continuous command processing capability.
Solution Approach 2:
By segmenting the buffer block into master and slave portions and updating mapping tables in separate sub-intervals, the system maintains mapping accuracy for the active buffer while the other buffer continues to process commands, thus preserving operational fluency without sacrificing reliability.
Data Source
AI summary
A mapping table H2F update technique for a FLASH memory is disclosed. In the disclosed data storage device, when a master buffer block selected from a plurality of blocks of a FLASH memory to buffer write data from a host is full, the controller updates a logical-to-physical address mapping table for the master buffer block in separated update sub-intervals. Between the separated update sub-intervals, the controller responds to commands from the host. In this manner, commands from the host are responded to in a timely manner, without being postponed by a time-consuming mapping-table update of an entire buffer block.