Hardware Accelerator for Flash Memory Read Address Translation
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Solution Overview
Problem
The performance of read operations in flash memory modules is degraded due to the need for address conversion between small block addresses used by host systems and large block addresses used by the flash memory module, which increases the time required for operations and degrades overall memory card performance.
Innovation Solution
A memory card with a memory controller that includes a hardware accelerator to convert external addresses into internal addresses, allowing for faster read operations by eliminating the need for continuous address conversion during read commands, especially in sequential and random read modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address conversion between small block addresses and large block addresses is performed using software routines, then compatibility between host systems and flash memory module is maintained, but read operation time increases and performance degrades
Solution Approach 1:
The patent replaces the software-based address conversion mechanism with a hardware accelerator circuit that performs address translation in parallel. The hardware accelerator includes an address translation look-aside table (ATLAS) and dedicated logic circuits that convert small block addresses to large block addresses without involving the main CPU, thereby maintaining compatibility while significantly reducing conversion time.
Solution Approach 2:
The hardware accelerator acts as an intermediary component between the host system and the flash memory module. It receives small block addresses from the host system, translates them to large block addresses through its internal ATLAS and translation logic, and outputs the converted addresses to the flash memory interface, thus mediating the address format discrepancy without affecting either end.
2Speed
If a hardware accelerator is added to perform address conversion, then read operation speed is improved, but device complexity increases
Solution Approach 1:
The memory controller is segmented into functional modules: a main CPU for general control, a dedicated hardware accelerator for address conversion, and a flash memory interface unit. The hardware accelerator itself is segmented into an ATLAS storage component and a translation logic component. This modular segmentation allows the address conversion function to be implemented as a separate, optimized unit that does not increase overall system complexity proportionally.
Solution Approach 2:
The hardware accelerator is designed to handle multiple address conversion scenarios including sequential reads, random reads, and boundary cases. The ATLAS structure can accommodate various address translation patterns, making the hardware accelerator a universal solution that handles different access modes without requiring additional specialized circuitry for each mode.
Data Source
AI summary
A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.