Flash Memory Access Management with L2P and P2L Table Checking
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Solution Overview
Problem
The management of data access in memory devices, particularly in Flash memory, is complicated by the mixing of invalid and valid data, leading to increased processing times due to the need for searching operations before reading data, and there is a lack of effective solutions in existing technologies.
Innovation Solution
A method and apparatus for data access management in a predetermined communications architecture using multi-table checking, involving a memory controller that utilizes both logical-to-physical and temporary physical-to-logical address mapping tables to optimize data reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If garbage collection is performed to release storage space, then storage space availability is improved, but processing time increases
Solution Approach 1:
The system performs preliminary actions by maintaining multiple address mapping tables (L2P and P2L) in advance, and pre-positioning valid data in optimized locations before they are needed. This allows the memory controller to quickly determine data validity and location without performing time-consuming garbage collection operations at the moment of data access.
2Reliability
If searching operation is performed before reading data, then data access accuracy is improved, but total processing time increases
Solution Approach 1:
The address mapping function is segmented into two separate tables: L2P table for logical-to-physical address mapping and P2L table for physical-to-logical address mapping. This segmentation allows the system to perform parallel or selective checking of different table types, reducing the time required for address verification while maintaining data access accuracy.
Solution Approach 2:
Instead of performing a complete exhaustive search before every data read, the system performs partial checking by first consulting the P2L table for active blocks. If the data is found to be valid in the P2L table, the system can directly access it without further searching. This partial action approach reduces processing time while ensuring accurate data access.
3Speed
If multiple address mapping tables are checked, then data access speed is improved, but device complexity increases
Solution Approach 1:
The system merges the functionality of multiple address mapping tables (L2P and P2L) into a unified address management structure that works together seamlessly. The memory controller integrates both tables and their respective checking mechanisms into a single coordinated system, reducing the operational complexity despite having multiple tables.
Solution Approach 2:
The P2L table acts as an intermediary structure between the L2P table and the actual data storage. It provides an additional layer of abstraction that simplifies the access process by pre-identifying valid data locations, thereby reducing the complexity of direct L2P table queries and improving access speed.
Data Source
AI summary
A method for performing data access management of a memory device in predetermined communications architecture with aid of multi-table checking and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first command from a host device, wherein the first command indicates that reading first data at a first logical address is requested; checking at least one logical-to-physical (L2P) address mapping table to generate a first checking result and starting performing a first read operation according to the first checking result, and checking a temporary physical-to-logical (P2L) address mapping table corresponding to a first active block to generate a second checking result for selectively performing a second read operation according to the second checking result; and returning the first data to the host device, wherein the first data is read according to one of the first checking result and the second checking result.