Flash Memory ECC Partitioning for Adaptive BCH Error Correction
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Solution Overview
Problem
Flash memory devices face reduced reliability and shorter lifetimes due to destructive program and erase operations, leading to errors exceeding the correction capability of existing error-correction codes, resulting in premature abandonment of memory blocks despite functional cells.
Innovation Solution
An adaptive-rate BCH error-correction scheme is implemented in non-volatile memory, where blocks are divided into partitions with user and parity data, allowing for variable correction capability and additional parity data storage, enabling efficient error correction and extending device lifetime by dynamically adjusting error correction modes and distributing extra parity pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory uses ECC for improving reliability and endurance, then error correction capability is improved, but the lifetime of the memory device still decreases due to destructive program and erase operations
Solution Approach 1:
The patent implements dynamic adjustment of error correction capability by changing codeword length based on the number of errors detected in memory blocks. The system transitions from fixed ECC parameters to adaptive parameters that respond to actual memory degradation states, allowing the memory device to maintain optimal error correction as it ages
Solution Approach 2:
The patent changes the parameters of the error correction code (codeword length, message length, parity length) based on the error conditions detected in memory blocks. By adjusting these parameters dynamically, the system adapts the error correction capability to match the actual degradation level, extending the usable lifetime of the memory device
2Reliability
If the entire flash memory module is abandoned when errors exceed correction capability, then data integrity is maintained, but most functional memory cells are wasted
Solution Approach 1:
The patent divides the flash memory into multiple blocks with independent error correction capabilities. When errors exceed correction capability in one block, only that specific block is marked as bad and abandoned, while other blocks continue to function. This segmentation prevents catastrophic loss of the entire memory module and maximizes utilization of functional memory cells
Solution Approach 2:
The patent implements a selective discarding mechanism where only degraded memory blocks are abandoned rather than the entire memory module. The system recovers and continues using functional blocks, thereby minimizing waste of memory resources while maintaining data integrity through continued error correction in healthy blocks
3Ease of manufacture
If fixed codeword length is used for error correction, then implementation is simple, but adaptability to varying error conditions is limited
Solution Approach 1:
The patent transitions from fixed to dynamic codeword length based on detected error conditions. The system monitors memory block degradation and adjusts codeword length accordingly, providing adaptability to varying error conditions while maintaining a relatively simple implementation through algorithmic parameter adjustment rather than hardware complexity
Solution Approach 2:
The patent changes codeword length parameters dynamically based on the number of errors detected in memory blocks. By adjusting parameters such as codeword length, message length, and parity length according to actual error conditions, the system achieves versatility in handling different degradation levels while keeping the implementation approach relatively simple through parameter adaptation
Data Source
AI summary
A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.