Flash Memory Decoding with Adaptive Read-Level Selection
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Solution Overview
Problem
Flash memory introduces data errors due to manufacturing variations and aging, which existing error correcting codes like LDPC codes attempt to address but at the cost of adding latency to read operations.
Innovation Solution
A method that selects a preliminary read-level voltage based on a decoding success indicator, performs a preliminary hard decoding operation, and if unsuccessful, executes a multi-stage decoding operation using a sequence of read-level voltages, allowing for efficient error correction without unnecessary latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used for error correction in flash memory, then error correcting capability is improved, but read operation latency increases
Solution Approach 1:
The patent performs a preliminary hard decoding operation using a selected read-level voltage before executing the full multi-stage decoding operation. This preliminary action identifies cases where simple decoding suffices, avoiding the latency of complete multi-stage decoding for those cases while maintaining error correction capability for more difficult cases.
Solution Approach 2:
The patent segments the decoding process into multiple stages: a preliminary hard decoding stage using a selected read-level voltage, and a multi-stage decoding operation that processes multiple read-level voltages sequentially. This segmentation allows the system to handle easy cases quickly and reserve comprehensive processing for difficult cases.
2Reliability
If multi-stage decoding operation is executed for all data, then error correction reliability is improved, but processing time increases
Solution Approach 1:
The patent applies partial action by executing only the necessary decoding stages for each data set. Instead of always performing the complete multi-stage operation, the system selects a preliminary read-level voltage and performs hard decoding first, executing additional stages only when the preliminary decoding fails, thus avoiding excessive processing for cases that require minimal correction.
Solution Approach 2:
The patent changes the parameter of read-level voltage selection dynamically. A preliminary read-level voltage is selected from a sequence based on decoding success indicators, and this voltage selection is adjusted according to the state of memory cells (fresh vs. aged), allowing the system to optimize between speed and reliability based on actual conditions.
3Loss of time
If preliminary hard decoding is performed before multi-stage decoding, then latency is reduced for successful cases, but system complexity increases
Solution Approach 1:
The patent introduces a preliminary hard decoding operation that uses a selected read-level voltage to quickly assess whether data can be decoded successfully. This preliminary action simplifies the overall process by identifying cases that don't require complex multi-stage decoding, reducing average latency while adding only a simple selection and initial decoding step.
Data Source
AI summary
Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.