Flash Memory Programming Using Adaptive Voltage Steps and Verify Times
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Solution Overview
Problem
Flash memory devices face challenges in achieving narrow threshold-voltage distribution profiles due to fixed programming voltage steps and verifying times, leading to inefficient programming times and potential miss-detection of memory cell states.
Innovation Solution
Implementing a control circuit that adjusts programming voltage steps and verifying times, using a first stair step sequence with a larger incremental step and shorter verifying time, followed by a second sequence with a smaller incremental step and longer verifying time, once a memory cell is verified as 'passed', to improve threshold-voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large programming voltage step is used, then programming speed is improved, but threshold-voltage distribution profile width increases
Solution Approach 1:
The programming operation is divided into multiple loops with different voltage step sizes. Early loops use larger voltage steps for rapid programming, while later loops use smaller voltage steps for precision control. This segmentation allows the system to achieve both high programming speed and narrow threshold-voltage distribution profiles by adapting the voltage step size to the programming stage.
Solution Approach 2:
The programming voltage step size is made dynamic rather than fixed. The control circuit adjusts the voltage step size based on the current programming loop number and verification results. This dynamic adjustment enables the system to optimize between speed and precision at different stages of the programming process, resolving the contradiction between programming speed and threshold-voltage distribution profile width.
2Device complexity
If a fixed verifying time is used, then device complexity is reduced, but measurement precision of memory cell state deteriorates
Solution Approach 1:
The verifying time is made dynamic and adaptive rather than fixed. The control circuit adjusts the verifying time based on the programming loop number and the detected memory cell states. This dynamic verification time allows the system to maintain high measurement precision for memory cells with threshold voltages close to the verifying voltage, while keeping the overall system complexity manageable through automated adaptation.
Solution Approach 2:
The verification process uses feedback from sense amplifier readings to dynamically adjust subsequent verification times. When memory cells are detected with threshold voltages close to the verifying voltage, the system increases verification time to improve detection accuracy. This feedback mechanism resolves the contradiction between verification complexity and measurement precision by using intelligent adaptation rather than fixed parameters.
3Measurement precision
If verification time is increased for cells near verifying voltage, then measurement precision is improved, but programming time increases
Solution Approach 1:
The programming and verification process is segmented into multiple loops with progressively smaller voltage steps. Each loop performs verification on a subset of memory cells, allowing the system to apply longer verification times only when necessary (for cells near the verifying voltage) rather than to all cells throughout the entire programming process. This segmentation reduces the overall time loss while maintaining measurement precision where needed.
Solution Approach 2:
The system applies extended verification time partially, only to memory cells whose threshold voltages are detected to be close to the verifying voltage. For cells clearly above or below the verifying voltage, standard verification time suffices. This partial application of excessive verification action maintains measurement precision for critical cells while minimizing the overall programming time penalty.
Data Source
AI summary
Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.