Flash Memory Readout Using Multi-Level ADC Error Correction
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Solution Overview
Problem
Multi-level solid state non-volatile memory systems face increased errors due to reduced signal distance between voltage levels, leading to reduced noise margin and higher error rates compared to conventional binary storage cells.
Innovation Solution
Implementing an analog-to-digital converter and error correction techniques that encode and decode data to increase the number of digital levels, utilizing modulation and encoding schemes adapted to the voltage constraints of solid state non-volatile memory systems, and employing convolutional codes and trellis coded modulation to enhance signal-to-noise ratio and error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells are used to increase storage density, then storage capacity increases, but signal distance between voltage levels decreases leading to higher error rates
Solution Approach 1:
The patent transforms the digital readout process by introducing an analog-to-digital converter that outputs more levels than the memory cell stores. This parameter change in the readout system allows the memory cell to operate at higher density while the enhanced readout provides sufficient resolution to distinguish between closely spaced voltage levels, thereby maintaining reliability despite reduced signal distance.
Solution Approach 2:
The patent introduces an analog-to-digital converter as an intermediary component between the multi-level memory cell and the digital processing system. This intermediary transforms the analog voltage levels from the memory cell into a higher-resolution digital signal, enabling accurate retrieval of data from densely packed voltage levels without direct digital-to-digital comparison that would fail due to reduced signal distance.
2Quantity of substance
If more quantization levels are stored in each cell, then storage capacity increases, but noise margin decreases making the cell more prone to errors
Solution Approach 1:
The patent changes the parameter of readout resolution by using an analog-to-digital converter that produces more digital levels than the number of stored quantization levels. This allows the system to detect subtle voltage differences with higher precision, effectively compensating for the reduced noise margin that results from storing more bits per cell.
3Device complexity
If conventional digital readout is used for multi-level cells, then system complexity remains low, but error correction capability is insufficient
Solution Approach 1:
The patent introduces an analog-to-digital converter as an intermediary that bridges the gap between simple multi-level memory cells and the need for robust error correction. This intermediary provides high-resolution digital output that enables sophisticated error correction algorithms to function effectively, achieving high reliability without requiring complex hardware modifications to the memory cell array itself.
Data Source
Figure 1~2C
Figure 3A
Figure 3B
AI summary
A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.