Flash Memory Error Correction Using Multi-Level ADC Quantization
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Solution Overview
Problem
Multi-level solid state non-volatile memory systems face increased errors due to reduced signal distance between voltage levels, leading to reduced noise margin and higher error rates, especially in read operations.
Innovation Solution
The implementation of an analog-to-digital converter and advanced encoding and decoding techniques, such as convolutional codes and trellis-coded modulation, to increase the number of digital levels in the output signal, improving data reliability and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells are used to increase storage density, then storage density is improved, but signal distance between voltage levels is reduced leading to higher error rates
Solution Approach 1:
The patent changes the parameter of digital signal levels from the conventional 4 levels to 16 levels by using an analog-to-digital converter with 16 quantization levels. This allows the system to distinguish between 16 different voltage levels, providing sufficient separation even when storage density is increased to 4 bits per cell, thereby reducing error rates while maintaining high storage density
Solution Approach 2:
The patent introduces an analog-to-digital converter as an intermediary component between the multi-level memory cell and the digital processing system. This converter with 16 output levels acts as a mediator that enhances the distinction between adjacent voltage levels, allowing reliable reading of 4-bit data from each memory cell without direct digital sampling
2Quantity of substance
If the number of quantization levels in memory cells is increased to store more bits per cell, then storage density is improved, but noise margin is reduced making the system more prone to errors
Solution Approach 1:
The patent changes the parameter of quantization levels from 4 to 16 in the analog-to-digital converter. This creates 16 distinct digital levels that provide sufficient noise margin even when the memory cell stores 4 bits per cell with only 4 voltage levels, effectively protecting against noise and errors
3Device complexity
If conventional 4-level quantization is used in multi-level memory, then device complexity is kept simple, but error correction capability is insufficient
Solution Approach 1:
The patent changes the parameter of digital output levels from 4 to 16 by modifying the analog-to-digital converter. This provides 16 distinct digital levels that enable sophisticated error correction algorithms to operate effectively, significantly improving error correction capability while the added complexity remains confined to the converter component
Data Source
AI summary
A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.