Flash Memory Error Correction Using Multi-Level ADC Readout
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Solution Overview
Problem
Multi-level solid state non-volatile memories face increased errors due to reduced signal distance between voltage levels, leading to reduced noise margin and increased susceptibility to erroneous readouts, especially in low-level signals with larger noise distributions.
Innovation Solution
The implementation of an analog-to-digital converter and advanced encoding and decoding techniques, such as convolutional codes and trellis-coded modulation, to increase the number of digital levels in the output, thereby improving data reliability and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level encoding is used to increase storage density, then storage density is improved, but signal distance is reduced leading to increased errors
Solution Approach 1:
The patent transforms the analog read signal from multi-level quantization into a higher-level digital signal (e.g., 4-level to 16-level or 32-level). This parameter transformation increases the effective signal distance and noise margin without changing the physical memory cell structure, thereby improving reliability while maintaining the high storage density achieved through multi-level encoding.
Solution Approach 2:
The patent introduces an analog-to-digital converter as an intermediary component between the multi-level memory cell and the digital processing system. This converter expands the limited multi-level signal into a higher-resolution digital representation, effectively bridging the gap between the compact multi-level storage and the reliable digital processing domain.
2Reliability
If conventional binary encoding is used, then noise margin is maintained, but storage density is limited
Solution Approach 1:
The patent adds a dimensional transformation by converting the multi-level analog signal into a higher-dimensional digital representation. Instead of directly using the limited multi-level states for digital processing, the system maps these states into an expanded digital domain with more levels, effectively adding a dimension of resolution that preserves noise margins while enabling higher storage density.
3Reliability
If analog-to-digital conversion with increased levels is implemented, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the analog-to-digital conversion process into distinct functional blocks: sense amplifier for reading the multi-level signal, analog-to-digital converter for expanding the signal levels, and processing logic for error correction. This segmentation allows each component to be optimized independently and facilitates integration into existing memory architectures, reducing the practical complexity despite the advanced functionality.
Data Source
AI summary
A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.