Flash Memory Address Buffer Circuit for Rapid Random Access
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Solution Overview
Problem
NOR flash memory devices require a delay known as the initial read time between each address input for random read operations, limiting the speed of continuous random read operations due to the need for a separate initial read section for each address input.
Innovation Solution
A flash memory device with an address buffer circuit, a read circuit, and a control logic that allows simultaneous storage and processing of multiple addresses, enabling the sensing operation for new addresses during the data output phase of previous addresses, thus overlapping initial read sections with data output sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a NOR flash memory device performs a sensing operation for each input address sequentially, then data can be accurately sensed and output, but the initial read time delay between each address input limits the speed of continuous random read operations
Solution Approach 1:
The patent stores multiple addresses in advance in an address buffer circuit before the sensing operation is needed. When a read operation is initiated, the addresses are already prepared and queued, allowing the sensing operation to proceed without waiting for sequential address input. This preliminary preparation of addresses eliminates the initial read time delay between consecutive read operations.
Solution Approach 2:
The patent enables continuous random read operations by overlapping the data output phase of one address with the sensing operation of the next address. While data from the first address is being output, the sensing operation for the second address occurs simultaneously, eliminating idle time and maintaining continuous useful action throughout the read sequence.
2Productivity
If the flash memory device waits for data output to complete before starting the next sensing operation, then data integrity is maintained, but the overall read time for continuous operations increases
Solution Approach 1:
Multiple addresses are pre-loaded into the address buffer circuit before the read operation sequence begins. This preliminary action ensures that when data output for one address is completing, the next address is already ready in the buffer, allowing immediate transition to the next sensing operation without waiting time.
Solution Approach 2:
The system maintains continuous useful action by overlapping operations: while data from address N is being output to external devices, the sensing operation for address N+1 proceeds simultaneously using the pre-loaded address from the buffer. This eliminates idle periods and maximizes productivity in continuous random read operations.
Data Source
AI summary
A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read circuit configured to sense data from the memory cell array in response to an address output from the address buffer circuit, an output data latch circuit configured to receive data sensed by the read circuit, and a control logic coupled to the address buffer circuit, the read circuit, and the output data latch circuit, and configured to control the output data latch circuit and the read circuit such that the output data latch circuit outputs first data read from the memory cell array substantially simultaneously as the read circuit senses second data from the memory cell array.