Flash Memory Wear Leveling via Logical Address Swapping
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Solution Overview
Problem
Flash memory devices face reduced durability and performance due to wear and tear, as the endurance of memory cells varies across different chips, leading to uneven wear leveling and potential performance imbalances between storage regions.
Innovation Solution
A data storage device with a scale-out structure that includes multiple volatile and non-volatile memory sets, utilizing a controller to swap logical addresses between storage regions based on wear counts, thereby implementing global wear leveling and balancing performance across clusters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in flash memory chips with varying endurance, then storage capacity is achieved, but durability and performance become unbalanced due to uneven wear
Solution Approach 1:
The flash memory storage system is divided into multiple independent multi-chip sets, each managing its own volatile and non-volatile memory. The controller segments the storage space into multiple storage regions across different chips, allowing independent wear management for each region. This segmentation enables the system to address wear issues at the regional level rather than affecting the entire storage system.
Solution Approach 2:
The controller dynamically changes the logical address mapping parameters by swapping logical addresses between storage regions based on wear count metrics. When a storage region reaches a certain wear threshold, the controller modifies the address translation table to redirect new data to less worn regions, effectively changing the operational parameters of the storage system to maintain balanced wear distribution.
2Quantity of substance
If multiple flash memory chips are used to increase storage capacity, then storage volume is improved, but overall durability is determined by the weakest chip
Solution Approach 1:
The storage system is organized into multiple multi-chip sets where each set independently manages its own volatile memory, non-volatile memory, and core controller. This segmentation isolates wear issues to specific chips rather than affecting the entire system, allowing the system to maintain operational integrity even when individual chips degrade.
Solution Approach 2:
The controller merges multiple storage regions from different multi-chip sets into a unified logical address space. By combining the capabilities of multiple chips with varying endurance characteristics and implementing global wear leveling across all merged regions, the system achieves both increased storage capacity and improved overall durability through balanced wear distribution.
3Reliability
If wear leveling is implemented at the chip level, then local durability is improved, but performance imbalance persists between different storage regions
Solution Approach 1:
The controller implements a universal wear management system that operates across all multi-chip sets and storage regions simultaneously. The same wear leveling algorithms and address swapping mechanisms are applied universally throughout the entire storage system, ensuring consistent performance characteristics across all regions regardless of their individual wear states.
Solution Approach 2:
The controller acts as an intermediary layer between the host and the multiple storage regions. It maintains a global view of wear counts across all chips and regions, and mediates data placement decisions by swapping logical addresses to direct data to the most appropriate storage region. This intermediary function balances performance across regions while maintaining local durability through coordinated wear leveling.
Data Source
AI summary
A data storage device includes a first multi-chip set which includes a first volatile memory, a first non-volatile memory, and a first core configured to control the first volatile memory and the first non-volatile memory, a second multi-chip set which includes a second volatile memory, a second non-volatile memory, and a second core configured to control the second volatile memory and the second non-volatile memory. A controller is connected to the first multi-chip set and the second multi-chip set and configured to swap a first logical address of a first storage region of the first non-volatile memory with a second logical address of a second storage region of the second non-volatile memory.