Flash Memory Soft Decoding Using Aggressor Bit Information

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Solution Overview

Problem

Existing memory devices face challenges in ensuring reliable access control, particularly under extreme conditions such as sudden power failures and temperature variations, which can lead to data loss and reduced storage capacity due to instability issues in multiple level cell (MLC) flash memories.

Innovation Solution

A method utilizing aggressor bit information to perform soft-decoding operations, where the memory controller reads data from adjacent pages to adjust decoding information, ensuring data recovery and maintaining storage capacity without introducing side effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MLC flash memory is used to increase storage capacity and reduce cost, then recording density is improved, but data stability and reliability deteriorate under extreme conditions

Engineering Contradiction:

Improverecording densityVSAvoiddata stability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces an intermediary error correction mechanism that mediates between the unstable MLC memory cells and the data integrity requirements. The error correction code acts as a buffer that compensates for the inherent instability of MLC memory under extreme conditions, allowing high-density storage while maintaining reliability through active error correction rather than passive tolerance

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the operational parameters of the memory system by implementing dynamic voltage threshold adjustment and adaptive error correction thresholds. Instead of using fixed parameters, the system adjusts voltage levels and correction thresholds based on detected error patterns and environmental conditions, enabling reliable operation of MLC memory across varying temperature and voltage conditions

Inventive Principle:

Principle #35Parameter changes

2Reliability

If traditional access control mechanisms are used in memory devices, then basic data protection is provided, but data recovery capability deteriorates under sudden power failure or extreme temperature variation

Engineering Contradiction:

Improvedata protectionVSAvoiddata recovery capability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements preliminary action by pre-calculating and storing error correction codes before data is written to memory, and by maintaining redundant parity information in dedicated protection pages. This preliminary preparation ensures that when power failure or extreme conditions occur, the recovery process can proceed using pre-computed correction data rather than attempting complex real-time recovery

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent employs feedback mechanisms where the system continuously monitors read operations and error patterns, then adjusts error correction strategies accordingly. When errors are detected during reading, the system feeds this information back to modify subsequent correction attempts, creating an adaptive recovery process that improves with each detection cycle rather than following a fixed recovery protocol

Inventive Principle:

Principle #23Feedback

3Adaptability or versatility

If aggressive error correction procedures are implemented to recover data under extreme conditions, then data recovery capability is improved, but available storage capacity deteriorates due to bad block formation

Engineering Contradiction:

Improvedata recovery capabilityVSAvoidavailable storage capacity

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent segments the storage space into data pages and separate protection pages, with further segmentation into multiple error correction layers. This segmentation allows the system to apply error correction selectively to specific pages rather than treating all storage uniformly, preserving capacity by only using correction mechanisms where needed while maintaining recovery capability for affected regions

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements partial error correction action by applying correction codes only to pages that exhibit error patterns, rather than universally correcting all data. The system performs excessive correction attempts only when necessary, using adaptive thresholds to determine when full correction procedures are warranted, thereby avoiding unnecessary capacity loss from conservative bad block marking

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11630590B1Method and apparatus for performing access control of memory device with aid of aggressor bit information

Publication Date: 2023.04.18 SILICON MOTION INC

AI summary

A method and apparatus for performing access control of a memory device with aid of aggressor bit information are provided. The method includes: receiving a first host read command from a host device; sending a first read command to the NV memory in order to try reading first data from a first page; sending a second read command to the NV memory to obtain soft-decoding information and performing a first soft-decoding operation according to the soft-decoding information in order to try obtaining the first data from the first soft-decoding operation; reading multiple bits from at least one aggressor page to be the aggressor bit information; converting the soft-decoding information into adjusted soft-decoding information according to the aggressor bit information of the at least one aggressor page; and performing a second soft-decoding operation according to the adjusted soft-decoding information to obtain the first data from the second soft-decoding operation.