Flash Memory Isolation Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing flash memory technologies face challenges in scaling down feature sizes, leading to issues such as increased parasitic capacitance and variation in electrical characteristics due to reduced dimensions.
Innovation Solution
Incorporation of air gaps in the isolation layer between gate stacks and active regions, achieved through doping the isolation layer to enhance etching uniformity and forming dielectric materials to reduce parasitic capacitance and improve electrical consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is scaled down to increase element density, then element density is improved, but parasitic capacitance increases and electrical characteristic variation worsens
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent memory cells and replaces it with air gaps. By removing the solid dielectric material from the isolation layer in regions between cells, parasitic capacitance is reduced while maintaining the benefits of scaled-down feature sizes for increased element density.
Solution Approach 2:
The patent introduces air gaps (porous structure) into the isolation layer to replace solid dielectric material. This porous configuration reduces the dielectric constant in regions between memory cells, thereby reducing parasitic capacitance while allowing continued scaling for higher element density.
2Quantity of substance
If feature size is scaled down to increase element density, then element density is improved, but electrical characteristic uniformity worsens
Solution Approach 1:
The patent applies different material compositions to different regions of the isolation layer. The first region (between cells) contains air gaps with lower dielectric constant, while the second region (under gate electrodes) maintains original dielectric material. This local differentiation reduces parasitic capacitance and improves electrical uniformity without compromising element density.
Solution Approach 2:
The isolation layer is segmented into multiple regions with different material compositions. The first region uses air-gap-filled dielectric material while the second region uses conventional dielectric material. This segmentation allows optimization of electrical characteristics in different areas while maintaining high element density through continued scaling.
3Object-affected harmful factors
If air gaps are formed in isolation layer to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent incorporates air gap formation into the existing isolation layer fabrication process by doping specific regions before dielectric material deposition. The doped regions are prepared in advance to enable selective removal, creating air gaps without requiring separate complex fabrication steps. This preliminary action reduces parasitic capacitance while minimizing increases in device complexity.
Solution Approach 2:
The patent changes the material parameters of the isolation layer by doping specific regions with phosphorus or arsenic. This parameter change creates regions with different etch selectivity, enabling selective removal to form air gaps. The parameter change approach integrates smoothly with existing fabrication processes, reducing parasitic capacitance without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gaps reduce parasitic capacitance and enhance uniformity of electrical characteristics across the flash memory device, improving data retention and reducing cross-talk between cells.
Implementation Method 1
partially recessing the doped isolation layer
Implementation Method 2
implanting a dopant into an upper portion of the isolation layer to form a doped isolation layer
Data Source
AI summary
A method for forming a flash memory includes forming an isolation layer to surround a plurality of active regions, forming a plurality of gate stacks across the active regions and the isolation layer, implanting a dopant into an upper portion of the isolation layer to form a doped isolation layer, partially recessing the doped isolation layer, and forming a dielectric material over the plurality of gate stacks, the plurality of active regions, and the doped isolation layer.