Flash Memory Analog Measurement Mode via JTAG
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Solution Overview
Problem
Current non-volatile Flash memory technologies face challenges in managing large embedded memory structures in System-on-Chip (SoC) devices, particularly below 28 nm lithography nodes, and require efficient signal exchange and measurement capabilities between memory and controller, with conventional JTAG protocols being slow and insecure.
Innovation Solution
Implementation of an internal analogic measurement mode in memory devices using a JTAG interface with a hardware block that includes voltage and current detectors, a Finite State Machine, and reference generators, ensuring accurate and secure measurement of voltage and current values with noise resistance and access control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional JTAG protocol is used for memory measurement, then measurement capability is provided, but measurement speed is slow
Solution Approach 1:
The patent extracts the measurement functionality from the standard JTAG interface and implements a dedicated measurement mode within the flash memory controller. This separates the measurement function from the general-purpose debug interface, allowing optimized measurement operations that are not constrained by the slow JTAG protocol timing requirements.
Solution Approach 2:
The patent introduces an intermediary measurement mode that sits between the JTAG interface and the flash memory array. This intermediary layer receives commands from JTAG, processes them through dedicated measurement circuits, and returns results, thereby enabling faster measurement operations than direct JTAG access would allow.
2Ease of operation
If measurement modes are made accessible for debugging, then measurement capability is improved, but security against hacking and reverse engineering deteriorates
Solution Approach 1:
The patent implements different access characteristics for different measurement functions. Critical measurement modes that could expose security vulnerabilities are restricted to authorized users only, while less sensitive measurement functions remain accessible for debugging. This localized differentiation of access rights maintains security while preserving necessary debugging capabilities.
Solution Approach 2:
The patent incorporates security measures that preemptively prevent unauthorized access to sensitive measurement modes. Access control mechanisms are built into the measurement mode activation process, requiring authentication or specific conditions to be met before certain measurement functions can be accessed, thereby preventing hacking and reverse engineering attempts before they can succeed.
3Measurement precision
If analogic measurement mode features are added to memory devices, then measurement accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines the analog measurement functions with the existing flash memory controller infrastructure. The measurement mode block integrates with the controller's existing voltage reference generators and timing circuits, sharing common resources rather than implementing completely separate measurement systems. This merging reduces the overall complexity increase that would result from adding dedicated analog measurement hardware.
Solution Approach 2:
The patent designs the measurement mode block to perform multiple functions: voltage measurement, current measurement, and various flash array characteristics measurement. By creating a universal measurement interface that can handle different measurement types through a single hardware block, the patent avoids the complexity of implementing separate dedicated circuits for each measurement function.
Data Source
AI summary
The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.