Flash Memory AND-Type Array for Dense, Low-Power Scaling
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Solution Overview
Problem
NOR-type flash memory faces limitations in scaling due to punch-through problems and increased power consumption as gate length is reduced, restricting integration and efficiency.
Innovation Solution
The flash memory employs an AND-type memory cell array structure with parallel connections between bit and source lines, utilizing Fowler-Nordheim tunneling for programming and erasing, allowing for reduced gate length and minimizing channel current, thereby achieving high integration and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate length is reduced to improve integration, then memory cell density increases, but punch-through problem occurs between source and drain
Solution Approach 1:
The patent replaces the conventional NOR-type memory cell structure with an AND-type memory cell structure. In the AND-type structure, the source and drain regions are connected in parallel between bit lines and source lines, eliminating the series connection that causes punch-through. This structural substitution allows gate length reduction without compromising reliability, as the parallel connection prevents direct current flow between source and drain through the channel.
Solution Approach 2:
The patent changes the connectivity parameter of the memory cell structure from series connection (NOR-type) to parallel connection (AND-type). This parameter change fundamentally alters the current flow path, allowing the gate length to be reduced while maintaining reliability. The parallel connection between source and drain regions enables this parameter change without causing punch-through problems.
2Area of moving object
If gate length is reduced to improve integration, then memory cell density increases, but power consumption increases due to channel current
Solution Approach 1:
The patent substitutes the NOR-type memory cell structure with an AND-type structure, where source and drain regions are connected in parallel. This substitution eliminates the channel current flow that causes power consumption, as the parallel connection prevents direct current path between source and drain. Consequently, power consumption is minimized while gate length can be reduced for higher density.
Solution Approach 2:
The patent converts the potential harmful effect of reduced gate length (which would normally increase channel current and power consumption) into a benefit by using the parallel connection structure. The parallel connection prevents channel current flow, so the reduced gate length for higher density does not result in increased power consumption. Instead, the structure turns what would be a harmful effect into a beneficial one.
3Productivity
If NOR-type memory cell structure is used to achieve high integration, then integration improves, but scaling approaches limit due to punch-through
Solution Approach 1:
The patent inverts the conventional NOR-type memory cell structure by using an AND-type structure with parallel connections. This inversion resolves the scaling limit problem because the parallel connection between source and drain regions eliminates the punch-through mechanism that limits NOR-type scaling. The inverted structure allows continued scaling without reliability concerns.
Solution Approach 2:
The patent replaces the NOR-type memory cell structure with an AND-type structure. This substitution enables continued scaling and improved integration without approaching the punch-through limit. The parallel connection in the AND-type structure fundamentally changes the current flow characteristics, allowing scaling to proceed without the reliability constraints that limit NOR-type memory cells.
4Productivity
If NOR-type memory cell structure is used, then high integration is achieved, but power consumption increases due to channel current during programming
Solution Approach 1:
The patent substitutes the NOR-type memory cell structure with an AND-type structure where source and drain are connected in parallel. This substitution eliminates channel current flow during programming operations, as the parallel connection prevents direct current path. Consequently, power consumption is significantly reduced while maintaining high integration levels achieved by the NOR-type structure.
Solution Approach 2:
The patent converts the potential harmful effect of channel current (which causes power consumption) into a benefit by using the parallel connection structure. In the AND-type structure, the parallel connection prevents channel current flow, so programming operations do not consume power through channel current. This converts what would be a harmful effect in NOR-type structures into a beneficial feature of the AND-type structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enables high integration and low power consumption by reducing gate length limitations and minimizing channel current, enhancing memory cell density and reducing parasitic capacitance.
Implementation Method 1
programming and erasing are performed by tunneling electrons between the channel and the charge storage layer of the selected memory cell
Data Source
AI summary
A flash memory capable of achieving high integration and low power consumption is formed by an AND-type memory cell array, an address buffer, a row selecting/driving circuit, a column selecting circuit, an input and output circuit, and a read/write control part. A memory cell includes, for example, a charge storage layer of an ONO structure. The read/write control part performs programming and erasing by Fowler-Nordheim (FN) tunneling between the charge storage layer and a channel of a selected memory cell.