Flash Memory Array Column Row Access Configuration
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Solution Overview
Problem
Existing flash memory systems are limited in their ability to access a greater number of flash memory cells simultaneously for read and programming operations, leading to slower performance compared to the need for faster access in modern computing and electronic devices.
Innovation Solution
The system allows for the simultaneous access of two columns or two rows in different sectors for read and programming operations, enabling twice as many flash memory cells to be accessed in a single operation compared to traditional systems, through the use of advanced circuitry and decoding techniques that minimize programming disturb across sectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional flash memory systems access one column or one row at a time, then programming disturb is minimized, but access speed is limited
Solution Approach 1:
The flash memory array is divided into multiple independently accessible columns and rows, allowing selective simultaneous activation of multiple columns or rows through dedicated decoders. This segmentation enables parallel access to multiple memory cells without requiring the entire array to be accessed at once, thus improving access speed while maintaining control over programming disturb.
Solution Approach 2:
The patent extends the traditional single-column-or-row access model by enabling simultaneous access along both column and row dimensions. Specifically, multiple columns can be accessed simultaneously with a single row, or multiple rows can be accessed simultaneously with a single column, creating a two-dimensional parallel access architecture that significantly increases throughput.
2Productivity
If multiple columns or rows are accessed simultaneously, then read and write speeds increase, but programming disturb across sectors may occur
Solution Approach 1:
The patent implements local quality control by applying programming inhibit voltages specifically to unselected columns and rows adjacent to the selected memory cells. This localized voltage control ensures that only the intended cells are programmed while neighboring cells in the same physical block are protected, maintaining sector isolation even during parallel access operations.
Solution Approach 2:
The patent introduces intermediary inhibit circuits and control logic that act as mediators between the parallel access pathways and the memory cells. These intermediary components monitor the selection status of each column and row, and selectively apply inhibit voltages to prevent unintended programming in cells that are not the target of the current operation, thus preventing programming disturb across sectors.
Data Source
AI summary
A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.