Flash Memory Array Separate Programming and Read Bit Lines
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Solution Overview
Problem
Flash memory arrays face challenges in operating with low programming voltages while maintaining low and predictable readout capacitance, as existing structures either require high voltages or result in unpredictable capacitance increases during readout, affecting performance and stability.
Innovation Solution
A separate programming bit line and read bit line configuration allows for low voltage programming and stable capacitance during readout, enabling efficient operation with transistors smaller than 0.18 microns and reducing variable capacitance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bit line is used for both programming and readout operations, then device complexity is reduced, but readout capacitance becomes unpredictable and increases during programming
Solution Approach 1:
The patent divides the bit line into two separate lines: a programming bit line (BLP) and a readout bit line (BLR). This segmentation allows independent optimization of each line's function, enabling low-voltage programming on BLP while maintaining stable, predictable capacitance on BLR during readout operations.
2Productivity
If high programming voltages are used, then programming effectiveness is improved, but transistor size must remain larger than 0.18 microns
Solution Approach 1:
The patent changes the voltage parameter by applying different voltages to different bit lines: the programming bit line receives high voltage (e.g., -8V) for effective programming, while the readout bit line operates at low voltage (e.g., -3V to -5V). This parameter differentiation enables the use of smaller transistors (below 0.18 microns) without compromising programming effectiveness.
3Length of moving object
If low programming voltages are used, then transistor size can be reduced below 0.18 microns, but programming effectiveness decreases
Solution Approach 1:
The patent applies local quality by providing different voltage conditions to different parts of the system: high voltage is applied locally to the programming bit line where programming occurs, while low voltage is applied to the readout bit line. This localized voltage differentiation allows small transistor sizes to be used while maintaining programming effectiveness through selective high-voltage application.
4Device complexity
If variable capacitance is present during readout, then data retrieval speed is affected, but device structure remains simpler
Solution Approach 1:
By segmenting the bit line into separate programming and readout lines, the patent eliminates the variable capacitance problem that occurs when a single line is used for both operations. The dedicated readout bit line maintains constant capacitance, ensuring stable and fast data retrieval without compromising structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables low voltage programming and stable capacitance during readout, improving the performance and reliability of flash memory arrays by allowing for smaller transistor sizes and maintaining predictable capacitance, thus enhancing data retrieval speed and accuracy.
Implementation Method 1
electrons will be diverted through the gate insulation 105 onto the floating gate 116 as a result of a phenomenon known as hot electron injection
Implementation Method 2
electrons will be diverted through the gate insulation 105 onto the floating gate 116 as a result of a phenomenon known as hot electron injection or Fowler-Nordheim tunneling or both
Data Source
AI summary
In a p-type flash memory array, separate programming and read bit lines are provided. The programming bit line is used only to program the floating gate transistors in the memory cells connected to that bit line. The read bit line is used only to read the state of a floating gate transistor in a selected memory cell connected to that bit line during the operation of the memory circuit. The resulting structure allows the use of low voltages during both programming and operation of the memory array. This makes possible the use of transistors in the memory array with feature sizes less than, for example, 0.18 microns. At the same time variable, unpredictable capacitances associated with each bit line in prior art p-type flash memory structures using comparable low programming voltages are eliminated when a particular memory cell attached to that bit line is being read out.