Flash Memory Array Byte Erasure via Coupling Capacitor
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Solution Overview
Problem
Conventional flash memory devices lack arbitrary random-access rewrite and erase operations, requiring the erasure of entire blocks to change a single byte, and incur high costs due to the number of additional masks needed for CMOS processes to embed flash cells and peripheral circuitry for high voltage signal generation.
Innovation Solution
A two-transistor flash memory array with PMOS floating gate-based non-volatile memory cells, utilizing a coupling capacitor and high voltage access transistors, allows for byte-level programming and erasure through Fowler-Nordheim tunneling, compatible with conventional CMOS technology and capable of withstanding high erase voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional flash memory erases entire blocks at a time, then manufacturing complexity is reduced, but operational flexibility and data retention are worsened
Solution Approach 1:
The patent segments the memory block into individually addressable memory cells that can be erased independently. Each cell contains a floating gate transistor with source and drain regions, allowing selective erasure of single bytes rather than requiring erasure of entire blocks. This segmentation enables arbitrary random-access rewrite and erase operations while maintaining manufacturing simplicity through standard CMOS processes.
2Reliability
If additional masks are used to embed flash cells in CMOS processes, then memory functionality is improved, but manufacturing cost and complexity are worsened
Solution Approach 1:
The patent uses universal CMOS transistors and standard CMOS fabrication processes to implement flash memory cells. The floating gate transistors are formed using standard CMOS device formation techniques, and the same CMOS transistors are used for both storage and high-voltage signal generation. This multi-functionality eliminates the need for additional specialized masks and processes, reducing manufacturing cost while maintaining full flash memory functionality.
Solution Approach 2:
The patent implements self-service by using the standard CMOS process itself to generate the high-voltage signals required for Fowler-Nordheim tunneling operations. The CMOS circuitry generates its own high-voltage signals internally, eliminating the need for external high-voltage generation circuits and additional manufacturing steps. This self-service approach reduces manufacturing complexity while maintaining complete flash memory operational capability.
3Ease of operation
If high voltage signals are routed through peripheral circuitry, then programming capability is improved, but device complexity is worsened
Solution Approach 1:
The patent merges the high-voltage signal generation function directly into the standard CMOS process. The same CMOS transistors and fabrication steps that create the memory cells also create the high-voltage signal generation capability. This merging eliminates separate peripheral high-voltage circuitry, reducing device complexity while maintaining full programming and erase capability through Fowler-Nordheim tunneling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables byte-by-byte programming and erasure, reducing the need for extensive reprogramming and improving data retention, while simplifying high voltage routing and reducing manufacturing complexity.
Implementation Method 1
Each of the memory cells comprises a floating gate memory transistor... Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, read, or inhibit a logic state stored by the memory transistor
Implementation Method 2
An EEPROM can be programmed and erased electrically using field emission (also known as 'Fowler-Nordheim tunneling'). In the erase method of a conventional EEPROM, stored electric charges will move from a floating gate and be removed due to the Fowler-Nordheim tunneling (F-N tunneling) effect.
Data Source
AI summary
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.