Flash Memory Array Architecture Sharing Data Path Circuitry

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Solution Overview

Problem

The existing flash memory architectures face challenges with the significant silicon area usage and performance impact due to the independent operation of fuse systems, which store operational information, leading to increased size and potential operational inefficiencies.

Innovation Solution

The integration of an information array with the memory array to share the same data path circuitry for programming, erase, and reading operations, with a power-on control circuit managing the information array's operation, allowing for the storage and retrieval of operating information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an independent fuse system is used to store operating information, then the information can be stored reliably, but the silicon area increases significantly

Engineering Contradiction:

Improveinformation storage reliabilityVSAvoidsilicon area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the fuse system with the main memory array by integrating the information array into the same physical structure. The information cells are coupled to the memory cells such that they share common word lines and bit lines, effectively combining two previously separate systems into one unified architecture.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared data path circuitry serves multiple functions: it can perform programming operations on both memory cells and information cells, erase operations on both types of cells, and reading operations on both. This multi-functionality eliminates the need for separate dedicated circuits for the fuse system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Loss of information

If an independent fuse system is used, then the operating information can be stored, but the device complexity increases

Engineering Contradiction:

Improveoperating information storageVSAvoidsystem architecture complexity

Core Design Contradiction:

Loss of informationVSDevice complexity

Solution Approach 1:

The control circuit is designed to control both the memory array and information array through a unified interface. The same control signals and data path are used for both arrays, reducing the complexity that would arise from having separate control circuits for each system.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of operation

If separate data path circuitry is used for fuse system, then the information can be accessed independently, but the silicon area and operational efficiency are degraded

Engineering Contradiction:

Improveindependent information accessVSAvoidsilicon area

Core Design Contradiction:

Ease of operationVSArea of stationary object

Solution Approach 1:

The shared data path circuitry is designed to handle both memory and information array operations through universal programming, erase, and read circuits. The same bit lines and word lines are used for both arrays, allowing independent access to information cells while sharing the physical infrastructure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7652905B2Flash memory array architecture

Publication Date: 2010.01.26 MACRONIX INTERNATIONAL CO LTD

AI summary

A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.