Flash Memory Array Segmentation for Threshold Voltage Control

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Solution Overview

Problem

Conventional flash memory devices face issues with wider distribution of threshold voltages and increased noise due to high current flow during data write operations, leading to potential transistor deterioration and reliability concerns.

Innovation Solution

A semiconductor memory device is designed with a memory array divided into first and second memory mats, where program pulses are applied sequentially to each mat, reducing the amount of current required and minimizing noise, and a write/verify control portion manages data write and verify operations to ensure accurate data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If program pulses are applied to all data write target bits in parallel until verify passes, then data write speed is improved, but threshold voltage distribution width increases and reliability deteriorates

Engineering Contradiction:

Improvedata write speedVSAvoidmemory cell transistor reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent divides the memory array into multiple sub-arrays and divides data write target bits into multiple groups, where each group is assigned to a different sub-array. Program pulses are applied sequentially to each sub-array rather than in parallel to all bits simultaneously. This segmentation approach maintains high data write speed by processing multiple groups while preventing excessive threshold voltage distribution width in any single group, thereby preserving memory cell transistor reliability.

Inventive Principle:

Principle #1Segmentation

2Manufacturing precision

If program pulses are applied multiple times to bits latest in threshold voltage shift, then data write completeness is improved, but threshold voltage distribution spreads wider

Engineering Contradiction:

Improvedata write completenessVSAvoidthreshold voltage distribution spread

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent segments data write target bits into multiple groups assigned to different sub-arrays. Bits that require multiple program pulse applications are distributed across different sub-arrays rather than concentrated in one sub-array. This ensures that bits latest in threshold voltage shift are not all subjected to multiple sequential program pulses in the same sub-array, preventing excessive threshold voltage distribution spread while maintaining data write completeness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the assignment of data write target bits to sub-arrays based on their threshold voltage characteristics. Bits requiring multiple program pulse applications are strategically distributed to different sub-arrays, while bits closer to verification are assigned to other sub-arrays. This dynamic assignment optimizes both data write completeness and threshold voltage distribution control.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If the entire memory array is processed as one unit, then device complexity is reduced, but noise increases due to high current flow

Engineering Contradiction:

Improvememory array structureVSAvoidnoise from current flow

Core Design Contradiction:

Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent divides the memory array into multiple independent sub-arrays, each capable of processing data write operations separately. This segmentation reduces the peak current flow in any single sub-array compared to processing the entire array as one unit, thereby reducing noise generation. The sub-arrays are controlled by separate control circuits that manage program pulse application independently, maintaining operational simplicity while reducing harmful noise effects.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach narrows the distribution width of threshold voltages and reduces noise, enhancing the reliability and efficiency of data write operations while minimizing the need for a large charge pump and reducing layout area.

Implementation Method 1

information of data '0' or '1' can be stored by applying a program pulse to a memory cell transistor of a memory cell in accordance with externally input data and varying a threshold voltage of the memory cell transistor utilizing channel hot electron (CHE) or Fowler-Nordheim (FN) tunneling

Methodology Applied

Scientific EffectChannel hot electron (CHE) tunneling:

Implementation Method 2

Methodology Applied

Scientific EffectFowler-Nordheim (FN) tunneling:

Data Source

PatentUS7652935B2Semiconductor memory device capable of achieving narrower distribution width of threshold voltages of memory cells and method of data write in the same

Publication Date: 2010.01.26 RENESAS ELECTRONICS CORP

AI summary

When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.